This change fixes USB and related different PHYs base address,
and interrupt. It also adds USB DBM and USB BAM related device
node and required resources for USB QDSS BAM functionality.
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
There is a deadlock scenario due to the circular dependency of CPU's
rq->lock and kswapd's waitqueue lock.
(1) when kswapd is woken up, try_to_wake_up() is called with it's
waitqueue lock held. It's previous CPU is offline, so it is woken
up on a different CPU. We try to acquire the offline CPU's rq->lock
in either cpufreq change callback or fixup_busy_time()
(2) At the same time, the offline CPU is coming online and init_idle()
is called from __cpu_up(). init_idle() calls __sched_fork() with
rq->lock held. A debug object allocation in hrtimer_init() called
from __sched_fork() is trying to wakeup the kswapd and attempts to
take the waitqueue lock held in the (1) path.
Task specific initialization is done in __sched_fork() and rq->lock
is not held when it is called for other tasks. The same holds true for
the idle task as well. __sched_fork() for the idle task is called only
when the CPU is not active.
Acquire the rq->lock after calling __sched_fork() in init_idle()
to fix this deadlock.
CRs-Fixed: 965873
Change-Id: Ib8a265835c29861dba571c9b2a6b7e75b5cb43ee
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
[satyap: trivial merge conflicts resolution and omitted changes for QHMP]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Enable configurations needed for the operation of data specific
features such as IPv4 and IPv6 tethering and packet filtering
using QoS. Enable ESP match target in iptables to provide the ability
to match packets based on the SPI (Security Parameters Index) value
in the ESP (Encapsulating Security Payload) header. Enable the
rmnet_data driver for MAP functionality.
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
This snapshot is taken as of msm-3.18 commit
d580948 (Merge "msm: ipa: fix race condition when teardown pipe")
Signed-off-by: Sungjun Park <sjpark@codeaurora.org>
IPC_LOGGING allows the debug logging for IPC Drivers and
QPNP_SMBCHARGER depends on EXTCON.
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Keep NR_CPUSs restricted to 16 compared to 64, since
some of the schedular tracer code has compile time
checks for NR_CPUS > 32.
Other options update in this defconfig is based on the
auto-update.
Change-Id: I91e28714e3ee79a06eb5994ad8fc14f0b58a1e43
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
It is found thats UFS device may take longer than 100ms to respond to
query requests and in this case we might run into following scenario:
1. UFS host SW sends a query request to UFS device to read an attribute
value. SW uses tag #31 for this purpose.
2. UFS host SW waits for 100ms to get the query response (and doorbell
to be cleared by UFS host HW).
3. UFS device doesn't respond back within 100ms hence UFS host SW times
out waiting for the query response.
4. UFS host SW clears the tag#31 from UTRLCLR register.
5. UFS host SW waits until UFS host HW to clear tag#31 from the doorbell
register.
6. UFS host SW retries the same query request on same tag#31 (sends a query
request to device to read an attribute value).
7. UFS host HW gets the query response from the device but this was
intended as a query response for the 1st query request sent (step-1).
8. Now UFS device sends another query response to host (for query request
sent @step-6).
Now there are 2 issues that could happen with above scenario:
1. UFS device should have actually responded back with only one query
response but it is found that device may respond back with 2 query
responses.
2. If UFS device responds back with 2 resposes on same tag, host HW/SW
behaviour isn't predictable.
To avoid running into above scenario, we would basically allow device
to take longer (upto 1.5 seconds) for query response.
CRs-Fixed: 966573
Change-Id: I9885cac614eff011b617064edcd31d0e8daddd45
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add snapshot for Video driver source for MSM targets. The code is
migrated from msm-3.18 kernel at the below commit level -
d5809484bb1bf5864dad2f081b0145224762963a.
Signed-off-by: Arun Menon <avmenon@codeaurora.org>
This change adds required QMP PHY related initialization from devicetree
instead of using getting revision based sequence from QMP PHY driver.
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
This change removes unused devicetree property with QMP PHY
as now all QMP PHY related initialization information needs to
be provided through devicetree.
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
This change updates USB QMP PHY related registers' offset from
devicetree for MSM8996 and cobalt platforms.
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
This change removes QMP PHY revision based phy_reg_offset from
QMP PHY driver. It makes mandatory to have required QMP PHY
related register offset through devicetree. It also removes
different revision ID related register offset usage and
requirement.
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
This change adds missing terminate entry with QMP PHY init sequence
which is required to know end of programming sequence.
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
This change removes QMP PHY revision based initialization sequence
from QMP PHY driver. It also makes mandatory to get this sequence
from devicetree except if qcom,emulation is set.
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
The core control module requires tracing capability. Export
a function that will allow new events to be added in an
extensible fashion without a compile-time dependency.
Change-Id: I807d1ec4a104d8289441512b61e5e26df291525b
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
The efficiency of a CPU can vary across SoCs depending on the cache size,
bus interconnect frequencies etc. Allow specifying this from the device
tree. This value overrides the default values hardcoded in the efficiency
table.
Change-Id: Ie9ba69e11317e6eb6462630226355747d1def646
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
On a HMP system, scheduler needs to know efficiency factor
(instructions-per-cycle) for various cpus. This is so that scheduler
can estimate bandwidth consumption of tasks on each cpu, based on
their efficiency factor.
This patch defines arch_get_cpu_efficiency() API in ARM64
architecture. It depends on hard-coded "efficiency" factor for
various cpu types (available in 'table_efficiency' data structure) and
device-tree providing information on cpu-type for every cpu.
Change-Id: Ied43ead650ab85b63c232bec14dde500cbcc0f7a
Signed-off-by: Srivatsa Vaddagiri <vatsa@codeaurora.org>
[joonwoop@codeaurora.org: s/SCHED_POWER/SCHED_CAPACITY/.]
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
In heterogeneous systems like big.LITTLE systems the scheduler will be
able to make better use of the available cores if we provide power numbers
to it indicating their relative performance. Do this by parsing the CPU
nodes in the DT.
This code currently has no effect as no information on the relative
performance of the cores is provided.
Change-Id: If025e959b523afa37e75d4c58578a7c5fea7e0b0
Signed-off-by: Mark Brown <broonie@linaro.org>
Patch-mainline: linux-arm-kernel 5/2/2014, 20:38
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
[joonwoop@codeaurora.org: s/SCHED_POWER/SCHED_CAPACITY/.
fixed a trival conflict in init_cpu_topology().]
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Add snapshot for msm_media_info video header to
uapi folder. The header file is taken from msm-3.18
kernel at commit - d580948 .
Signed-off-by: Arun Menon <avmenon@codeaurora.org>
This property is no longer used in 4.4 kernel, hence remove it.
Change-Id: I82dae3d9c230c9e6d71e4b286d5eba684d1511f8
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In commit 48924e2fe107 ("dwc3: Reset USB controller/PHY after psy
connect indication at bootup") the controller initialization path
was removed from dwc3_msm_probe() and is deferred to when actually
needed, which is when beginning peripheral or host mode. This was
to optimize for the HVDCP charger already-connected case in which
case we want to avoid performing controller initialization which
can disrupt D+/D- linestate.
As part of that change, the OTG_STATE_UNDEFINED state was made
to be the entry point for starting controller initialization.
However, apart from that, the handling is identical to B_IDLE_STATE,
and therefore could be consolidated. And now that charger driver
only notifies us when SDP or CDP types, but not when DCP/HVDCP are
connected, the code can be simplified by removing the duplicate code
between dwc3_initialize() and dwc3_msm_resume().
Change-Id: Ife749c864284864098bcbcbdbda096d05397c60e
Signed-off-by: Jack Pham <jackp@codeaurora.org>
dwc3_init_sm() uses a static boolean variable which does not
play nicely when multiple instances are in use. For instance
if one controller is configured in host-only mode, it would
set the sm_initialized flag and can force the second controller
to also see ID=0 and enter host mode even if it is a peripheral.
The false ID=0 is actually caused by the init sequence never
actually setting the initial inputs bit, so the state machine
simply sees it as unset and proceeds to the A_IDLE case. Fix this
by setting it to 1 to match the id_state=FLOAT during probe().
Furthermore, there is no longer any use case for the vbus_init
completion since the state machine should only be entered upon
event changes anyway. So removing that can allow us to get rid
of dwc3_init_sm() entirely. Also ensure that sm_work is
unconditionally flushed before processing the initial events.
CRs-Fixed: 974882
Change-Id: I48e361a622bffa62ab7fa4c8d2e6719e66b90076
Signed-off-by: Jack Pham <jackp@codeaurora.org>
On MSM8996 the PMI8998 charger requires the USB D+/D- to
be in floating state prior to performing charger detection.
Control of this is exposed by the QUSB PHY node and is
referenced by the charger as the dpdm-supply regulator.
Signed-off-by: Jack Pham <jackp@codeaurora.org>
The primary USB device now requires an extcon reference
for cable connection notification. On MTP & CDP targets
this is provided by the PMI8994 charger device.
Signed-off-by: Jack Pham <jackp@codeaurora.org>
The USB PHY no longer exports DP/DM control via power_supply.
Instead, use the regulator it exposes to replace the DPF_DMF
with regulator_enable() and DPR_DMR with regulator_disable().
All other operations (e.g. pulsing) are no-ops for now until
suitable replacements are available.
Signed-off-by: Jack Pham <jackp@codeaurora.org>
The USB power_supply object should be maintained by the
charger driver. Since it is now removed from the USB
controller driver, create and register it here. Many
of the calls to set/get_property can be simplified since
there are equivalent state variables we have access to.
PROP_OTG can be removed entirely since that is now handled
by emitting an EXTCON_USB_HOST notification.
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Allow charger to expose an extcon device which can emit
notification for USB and USB-HOST cable connection states.
The driver can correspondingly register interest in being
notified of these cable connection statuses.
This is intended to replace the power_supply_set_present()
and power_supply_set_usb_otg() mechanisms currently used.
Change-Id: I6c7cf971f59ac3f3075f5c8f13786306729f25a8
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Now that we use extcon for USB and USB_HOST cable connection
notification, it is no longer required to provide the usb
power_supply object in order to receive set property
notifications. Going forward the usb_psy will be maintained
by the charger driver(s) instead.
Since supply type is now also hidden from this driver (i.e.
EXTCON_USB should only be emitted in the case of SDP or CDP)
handling of dedicated charger types can also be removed which
simplifies the code a bit.
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Add extcon listeners for EXTCON_USB and EXTCON_USB_HOST cable
types to be notified of VBUS and ID notifications respectively.
Upon notification this will start the controller in either
peripheral or host mode.
This replaces the handling previously done in the power_supply
set_property() callback for PROP_PRESENT and PROP_USB_OTG. The
usb_psy will be removed in its entirety following this patch.
Change-Id: I22405a0a8da21b4c373895500d8dc4c91d97bc51
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Enable the EXTCON framework driver. This is used to allow
drivers to notify other drivers about various cable connection
state. For example the charger driver can notifiy USB driver
when a cable is connected or removed.
Change-Id: I07d12466bfe0b951769ec7d86a15af2811dbc390
Signed-off-by: Jack Pham <jackp@codeaurora.org>
On downstream kernels CONFIG_SWITCH may still be enabled
providing the Android switch class functionality. Although
extcon was intended to be the spiritual successor, allow
them to coexist for now, at least until the client drivers
have all migrated.
Signed-off-by: Jack Pham <jackp@codeaurora.org>
As RUMI platform uses QRBTC-V2 UFS PHY, we need to disable
various LPM modes so that UFS initialization is successful
due to hw limitations.
Change-Id: I7b7efc2fd6f01136a7f737d213e02e3aa078cbda
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Since msmcobalt RUMI uses QRBTC-V2 UFS PHY, there are a few limitations
that must be applied in order to be able to initialize UFS:
1. UFS should remain in PWM-G1 1-Lane and never change its gear, as other
gears are not stable
2. hibern8 enter/exit should be bypassed
3. we should avoid any power change (as in runtime suspend/resume)
Add "qcom,disable-lpm" property to facilitate disabling of these.
Change-Id: I3f1801da1e2bf1ce8ce98f5ab08211683106ae8c
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
We dump out the register information in case of UFS errors and
ICE debug registers are also generally needed to debug these errors.
This change calls into ICE driver's debug ops to print out the
ICE register dump in error scenarios.
CRs-Fixed: 960214
Change-Id: Ifed25208fab588985603bf418b4e77d90d13c440
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
If we issue the link startup to the device while its UniPro state is
LinkDown (and device state is sleep/power-down) then link startup
will not move the device state to Active. Device will only move to
active state if the link starup is issued when its UniPro state is
LinkUp. So in this case, we would have to issue the link startup 2
times to make sure that device moves to active state.
CRs-Fixed: 967639
Change-Id: I140560308262b9d5c184b9cac8d530fb384816d4
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
There's a deadlock between clock scaling and clock ungating work if hibern8
exit fails while ungating clocks.
ufshcd_exec_dev_cmd() in clock ungating work blocks at taking
"clk_scaling_lock" unless clock scaling work completes which had taken
"clock_scaling_lock" and it will never be released hence this is a
deadlock.
Clock ungating context:
----------------------
-000|__switch_to()
-001|context_switch(inline)
-001|__schedule()
-002|schedule()
-003|rwsem_down_read_failed()
-004|down_read()
-005|ufshcd_get_dev_cmd_tag(inline)
-005|ufshcd_exec_dev_cmd()
-006|ufshcd_verify_dev_init()
-007|ufshcd_probe_hba()
-008|ufshcd_host_reset_and_restore()
-009|ufshcd_link_recovery()
-010|ufshcd_uic_hibern8_exit()
-011|ufshcd_ungate_work()
-012|static_key_count(inline)
-012|static_key_false(inline)
-012|trace_workqueue_execute_end(inline)
-012|process_one_work()
-013|process_scheduled_works(inline)
-013|worker_thread()
-014|kthread()
-015|ret_from_fork(asm)
-->|exception
-016|NSX:0xF0440E59300(asm)
---|end of frame
Clock scaling context:
----------------------
-000|__switch_to()
-001|context_switch(inline)
-001|__schedule()
-002|schedule()
-003|schedule_timeout()
-004|do_wait_for_common(inline)
-004|__wait_for_common(inline)
-004|wait_for_common()
-005|wait_for_completion()
-006|flush_work()
-007|ufshcd_hold()
-008|ufshcd_hold_all()
-009|ufshcd_wait_for_doorbell_clr()
-010|ufshcd_clock_scaling_prepare(inline)
-010|ufshcd_devfreq_scale()
-011|ufshcd_devfreq_target()
-012|update_devfreq()
-013|devfreq_monitor()
-014|static_key_count(inline)
-014|static_key_false(inline)
-014|trace_workqueue_execute_end(inline)
-014|process_one_work()
-015|worker_thread()
-016|kthread()
-017|ret_from_fork(asm)
-->|exception
-018|NSR:0x2A714C(asm)
---|end of frame
This change is fixing this by moving ufshcd_hold_all() in
ufshcd_devfreq_scale() to the beginning of the function so that
clk_scaling_lock is acquired only after clock ungating completes.
CRs-Fixed: 963407
Change-Id: I83788c3212baeab31cf1bf877ca0aaf9005ca661
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
We want to request TZ to change page table format
for non secure context banks only if static-cb
option is enabled. If the option is disabled then
programming of global registers would be done by
HLOS itself and we need not request TZ to change
page table format.
Change-Id: Id2228e6d2ec835e169d679296760256ce0524050
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
For targets where we have slave side protection,
global register programming is handled by TZ. And
since it supports V7S page table format only, by
default TZ programs all context bank to permit
V7S format by programming VA64 bit of CBA2R register
as 0.
But if context bank itself is non secure then its
page tables are managed by HLOS where we can
support V8L page table format. So, provide a way
to request TZ to change page table format to V8L
for non secure context banks.
CRs-Fixed: 959535
Change-Id: I1f4d4b98c4f240a8351f791901abdfa78b829973
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
restore_sec_cfg call needs to be made to inform
secure world that device have resumed from power
collapse mode and security settings need to be
relaxed. Accordingly we had a restore_sec_cfg
call in arm_smmu_resume which would be called
from regulator_notifier on regulator enable
event.
But during initial device probe also we need to
read through SMMU global registers like IDR0,
IDR1 to understand hardware configuration of SMMU
and accordingly populate our data structures. We
can't call arm_smmu_resume at this point as we
are still to identify page size of SMMU register
map which we get only through reading IDR1
register.
So make an explicit restore_sec_cfg call at SMMU
probe which would enable us to read through
SMMU global registers. We need this call only
for targets which have slave side protection
mechanism.
CRs-Fixed: 959535
Change-Id: If4e53966edbf4e76a3d03f3a8684563f0ceac13d
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
When we have SMMU halt/resume functionality
enabled we try to program MICRO_MMU_CTRL register
which is part of SMMU implementation defined
register space. Now targets which have slave side
protection mechanism, implementation defined
register space of SMMU is protected by XPUs along
with other SMMU global register space. As a result
we would get a fault if we directly try to program
MICRO_MMU_CTRL register.
Instead we request TZ through atomic scm call to
program this register for us. Since we have read only
permission available for these registers we need to
ensure that write operation is requested through TZ.
CRs-Fixed: 959535
Change-Id: Ie257553a25bb11785b69568d8eccbef91d8d18e0
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
For targets where we have no hypervisor, slave
side protection mechanism is used to provide
buffer protection. Add functionality to make
calls into TZ for mapping/unmapping of buffers.
CRs-Fixed: 959535
Change-Id: I3106a98370a70611f4670aaf1c0f95c9e758a87c
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
To implement slave side protection, programming of
global registers as well as secure context bank
registers is handed over to TZ. Now, instead of
dynamically allocating context banks, TZ allocates
CBs once in pre defined static manner during boot
and this allocation is maintained throughout the
life of system.
Add an option to enable use of this pre-defined
context bank allocation. We would be reading
through SMR and S2CR registers at run time
to identify CB allocated for a particular sid.
CRs-Fixed: 959535
Change-Id: I782470a2e4d2a66be17ed2b965ba52b7917592f6
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
Up until now, the arm-smmu driver has only supported one type of
security mechanism: master-side access control. However, in the near
future it will be getting support for slave-side access control, at
which point saying a domain is "secure" will be ambiguous. Make the
distinction explicit by renaming arm_smmu_is_domain_secure to
arm_smmu_is_master_side_secure.
CRs-Fixed: 959535
Change-Id: Ie9bc077fe60d0b97c744fdb5b3f553cc056df27f
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
