Modify ACD_EXTINT_CFG so that ACD calibrates every time OSM toggles
full freq signal. This is recommended by hardware guidelines to
prevent ACD from mitigating when CPU clock frequency is boosted.
CRs-Fixed: 1088429
Change-Id: I07856ea8b332dbf12654fdd0b5d5518355f1c350
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add mem-acc threshold and crossover voltage properties to the
VDD_APC0/1 CPR devices and a matching mem-acc crossover voltage
to the OSM device. Update the APM threshold voltage
to 800 mV for both clusters.
CRs-Fixed: 1088429
Change-Id: I747fd7665401803998b2824ace6dedbc5797b17f
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support for configuring the highest memory accelerator
(MEM ACC) threshold voltage. This threshold voltage is used at
runtime to determine which CPRh virtual corner to program into
the OSM sequencer registers in place of the fixed MEM ACC
configuration specified in the OSM LUT.
CRs-Fixed: 1088429
Change-Id: Ida29eaca139c1ddd6439d11a8bd51526366f2a34
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for configuring the memory accelerator (MEM ACC)
threshold voltage and the MEM ACC crossover voltage.
The threshold voltage is used to restrict the floor to ceiling
voltage range of all corners so that they cannot cross the
the MEM ACC threshold voltage due to CPR operation. The
crossover voltage is set when switching the MEM ACC
configuration.
If specified, the APM and MEM ACC crossover voltages are added
to the array of corners after all true corners. If both are
specified, then the APM crossover corner is added before the MEM
ACC crossover corner (i.e. last corner = MEM ACC crossover and
second to last corner = APM crossover).
CRs-Fixed: 1088429
Change-Id: I2b9b746071579ba9d4bcdcfb6cb755ca08a73182
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for addtional performance cluster speed bins. Speed bin
fuse 2 and 3 devices can run with a quad core CPU fmax of 2.361 GHz and
single core CPU fmax of 2.457 GHz.
CRs-Fixed: 1086294
Change-Id: I08c3b8bc7e4d40c80be588f05b9439b339f46afc
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the VDD_APC0 and VDD_APC1 CPR devices to support two additional
speed bins. This allows CPR operation on bin 2 and 3 parts which have
different performance cluster frequency configurations compared to bin
0 and 1.
CRs-Fixed: 1086294
Change-Id: Id0854f1094ee3e4d4b1961f98a77003f7bcca1da
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The OSM LUT may have duplicate frequencies between one
and four core count compatible frequencies. If the selected
frequency exists for both single and quad core, select the quad
core frequency by default. Also, expose only 4-core frequencies
and the absolute maximum frequency to clock consumers.
CRs-Fixed: 1086294
Change-Id: I2424bfdfd381241d307862113451082a9727a903
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The values written into OSM sequencer registers #55 to #58
correspond to indexes into the CPRh virtual corner table not
indexes into the OSM table. Correct this.
Change-Id: I02baca9a410f08c82c34fe82925c0ead22111e5b
CRs-Fixed: 1086294
Signed-off-by: David Collins <collinsd@codeaurora.org>
The maximum VDD_APC1 voltage has been increased to 1.136 V
for msm8998 v2. Update the AVS limits of L2 SAW and the
CPR aging reference voltage to reflect this.
CRs-Fixed: 1086294
Change-Id: I863bee32e1e66d9656fc70748628b25606b59e47
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Support a total of 32 fuse combos to cater to MSM8998
parts blown with speed-bins 2 and 3.
CRs-Fixed: 1086294
Change-Id: Id03a418f66c9cbb51c2be6904f682d15e82f78c8
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the VDD_APC0/1 max floor to ceiling range as well
as the open-loop and closed-loop Nominal fuse corner
adjustments to match the latest hardware characterization.
CRs-Fixed: 1086294
Change-Id: I920175ab16d5a3fc5cd3f117bba3fd1d37db3c5d
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add the necessary configuration to the OSM clock device in
msm8998 v2 to initialize ACD.
Change-Id: Ibdb861a50ad654be34e14e2bcc012fdf5063acaf
CRs-Fixed: 1053383
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Perform a complete or adequate check of return codes for several
functions, including __qseecom_enable_clk, ion_do_cache_op and
ion_sg_table(), used by qseecom.
Change-Id: Ib1682bdc6d3034a22586af62a3d8986c54d369d5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
The clock nodes require the regulator nodes to be updated for interposer,
so add the same. Also update the gfx rail regulator phandle.
Change-Id: I08580f4eb04660cd1d123065976ba9bfec61b7d8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add the new perf configuration for msmfalcon and msmtriton.
Update the msmfalcon_defconfig also.
Change-Id: I8c3be2d0235395a338b758e4dc27a4b243bff62d
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
Fix some potential issues in HDMI driver such as suspicious
dereference of NULL pointer and variable reference without
initialization.
CRs-Fixed: 1091211
Change-Id: I81a99bcc4201ccd72de1f812e9c4da36d6a81958
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Add sysfs and ioctl to adjust HDMI clock rate by certain PPM.
This function is required by clock recovery in broadcast in
which HDMI PLL should be adjusted in order to reduce the clock
drift in broadcast.
CRs-Fixed: 1086894
Change-Id: I1df15dd6aec44ae3e78bd4f80dc70d0d04760687
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Before adding the irq affinity based qos request to the list, if
the affinity of the interrupt changes it will trigger notify call.
This notifier call will try to update the qos request. Accessing
the qos request which is not yet added to the list leads to a
NULL pointer exception.
Avoid this race by registering the notifier after adding the
qos request.
Change-Id: I99869cc233573b5db10e4f3224d65c29511050ea
Signed-off-by: Anil Kumar Mamidala <amami@codeaurora.org>
