Need to consider hardware pipe priority when validating an
atomic commit. Hardware requires certain source pipes to be
left-most compared to other source pipes when in source split
configurations.
CRs-Fixed: 2005394
Change-Id: I4a19fbe9f78db8e557720ef7973034fdbd2f8a58
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add checks to sde debug facility to reject poorly formed
register block ranges. Add names for dsc and vbif register
blocks. Register the vbif hw block under the vbif base register.
Fix the names of the printed register blocks to be 0 based as
expected. Fix the DSC register length initialization. Sort
register ranges before printing. Register mdp top block
address before dumping the sde debug bus.
Change-Id: I0179d59543de52537937abcc7d556f79569e9c55
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support for dumping the sde and vbif debug buses. Can be
triggered via sysfs, or via the SDE_DBG_DUMP macros by providing
"dbg_bus" or "vbif_dbg_bus" strings in the dump area list.
Change-Id: I8b3261a7bdc0161e77729ed0d05bf90cf9214298
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Need the capability to dump the content of sde registers during
panic and other scenarios. Add debugfs facility for triggering
register dumping. Add registration of sde and vbif as base
hardware blocks. Add the blocks within the sde as named register
dumping ranges.
CRs-Fixed: 2005394
Change-Id: I410c4e5270447d4d3a8364287fa61748ead5410f
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Need to read register block length from the DTSI and populate
into the catalog to support register debug dumping. Also add a
name string to each of the blocks for debug purposes.
CRs-Fixed: 2005394
Change-Id: Ia2299a51d649942b9335bc023d098d9c4882f1de
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Return value of snprintf doesn't account for the terminating
null character it appends to the end of every string.
So this change adds one extra character length to the blob size
to avoid over reading from the client end.
Change-Id: I8919f0b01dcbcad9300c28e070e9b9ca64368db2
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Sachin Bhayare <sachin.bhayare@codeaurora.org>
Map and pin buffers on demand on the submission path.
This ensures that we only map buffers whose iova are
actually needed for submission as opposed to all
buffers in the buffer list. For instance, the command
buffers, and the reloc buffers for processing relocs.
Also remove unused member valid from the struct
msm_gem_submit.
Change-Id: I644f44f202552d14762ffe1d1761b98ed5961020
Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
Map command buffers to the kernel address space only if
relocs are specified for the submission. This reduces some
overhead on the submission path.
Change-Id: I32ca3c7fe2147c835a328e0c8937b45f2f3d59b9
Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
Remove the incorrect Ainfo transfer to the sink during the
start of repeater test cases for the HDMI HDCP 1x module.
This causes incorrect results from sinks which are repeaters.
Fix the logic to disable software DDC before going into
part3 of HDCP 1x authentication.
Change-Id: Iddf1c5804162ecd3919a0d4fedc9102e3b1778ed
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Currently, deep color mode flags are not being cleared
across connect-disconnect of HDMI cable. This leads to
stale information being present on the next successful
connection.
Clear the stale deep color mode flags before updating the
modes during a connection event.
Change-Id: I90d494a67dfb1c3fd464f1e1ffb24592bd712702
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This patch addresses an issue in the GPU init sequence where
the clocks are turned on during the process but after the
init is complete the clocks are not turned off. Due to this,
the GPU clocks always have a refcount delta of 1 and never
get disabled later even when explicitly requested.
Change-Id: I40fa9a25cd86f5d39fbe6f6e3f83d6ab467d615f
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
After enabling the GPU clocks, the GPU can pagefault
when trying to access memory(example the ringbuffer).
This patch addresses the pagefault issue by enabling
the memory retention flags on the GPU core clock.
Change-Id: Ibabecba77501d6a3b188b19c90c172de7d667c8c
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Turn off the GPU power and free all resources allocated during
GPU init in case hardware init fails in adreno_gpu_load. This is
required to make sure further tries to load the GPU again doesn't
fail because of invalid GPU state.
Change-Id: I1d0d68f62be751d76274975e098364131712ca38
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
Add support to update the HDMI AVI infoframe to use
BT2020 encoding during HDR video playback.
This is required as per the spec to ensure that the
AVI infoframe correctly indicates the content being
shown.
Also make sure to change and restore the YCC
quantization bits in case of override.
Change-Id: Iadacc2fac6252b5f5cbfcc39a122118f738d3113
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
The CSC matrix used in the CDM block should be
updated to BT2020 format from the default value
during HDR video playback.
Add support in the SDE driver to enable switching
CSC matrix of CDM block to BT2020 during start of
HDR playback and restore it at the stop of the
playback to the default CSC.
Change-Id: Ic589380188ddef8ada2c8bbc0ca945bb1f319c85
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Currently only BT601 CSC matrix is available for use
in the SDE driver.
Add BT709, BT2020 CSC matrix definitions to SDE driver.
These shall be used during different use-cases such as
HDR video playback by switching the CSC matrix based on the
use-case.
Change-Id: I70a543193d08217cbdb6c4af739b3777dde4a25d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
CDM block is always using a limited quantization range
matrix.
This can be overridden to use a full range matrix if
the sink supports override capability or the mode is a
non-CEA mode.
Adjust the matrix selection logic to accommodate these
conditions.
Change-Id: I708412a923fb0d47e798f35ebe14b4c2f1a72fc9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Only HDMI INTF3 should need cdm block, other
INTFs do not need cdm.
Change-Id: Iff355dae456ed432efd84dff72ec85b83dbb93f2
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Sometimes, after user space is up and starts the handoff for early
animation/display, page freeing error happens like below.
The error happens in a very small possibility, but will lead to
device rebooting.
Call trace:
dump_backtrace+0x0/0x1b8
show_stack+0x14/0x1c
dump_stack+0xa8/0xe0
bad_page+0xf0/0x118
free_pages_prepare+0x100/0x2cc
free_hot_cold_page+0x38/0x1a0
__free_pages+0x34/0x48
_sde_splash_free_bootup_memory_to_system+0x78/0x9c
sde_splash_clean_up_free_resource+0xbc/0x1f0
sde_crtc_complete_commit+0x114/0x14c
sde_kms_complete_commit+0x50/0x98
complete_commit+0x684/0x6b0
_msm_drm_commit_work_cb+0x30/0x38
kthread_worker_fn+0xcc/0x170
kthread+0xf8/0x100
ret_from_fork+0x10/0x20
The issue is caused by race competition.
In async commit mode, the first is, mutex lock should be involved to
ensure the member of splash_info structure can be protected to
read/write in multiple threads. And the second is, 2 DSI connectors
are available in kernel, and the coming sequent commits may happen on
one DSI or on two DSI respectively. Because DSI interfaces shares the same
resource in LK, if the consecutive commits are for one DSI, DSI resources
could not be released, as another DSI is still visiting and using these
resources. So till confirming the commits for different DSIs have been
done, it's safe to release DSI resource.
Change-Id: Ie6386e3e58d5320cd4e2caab9a07b4e659eb8780
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Currently, when scrambler is disabled the TMDS clock ratio bit
is left untouched. Ideally the sink should reset this bit during
hot plug OR no-signal cases. However, the HDMI spec requires this
bit to be explicitly reset by the source.
Add support to reset this bit during scrambler disable.
Change-Id: I092f6cae84653940e2bdb9100df5e384084cf938
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
[ Upstream commit a6cb3b864b21b7345f824a4faa12b723c8aaf099 ]
For every submission buffer object one of MSM_SUBMIT_BO_WRITE
and MSM_SUBMIT_BO_READ must be set (and nothing else). If we
allowed zero then the buffer object would never get queued to
be unreferenced.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 88b333b0ed790f9433ff542b163bf972953b74d3 ]
Currently the value written to CP_RB_WPTR is calculated on the fly as
(rb->next - rb->start). But as the code is designed rb->next is wrapped
before writing the commands so if a series of commands happened to
fit perfectly in the ringbuffer, rb->next would end up being equal to
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
The easiest way to fix this is to mask WPTR when writing it to the
hardware; it makes the hardware happy and the rest of the ringbuffer
math appears to work and there isn't any point in upsetting anything.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
[squash in is_power_of_2() check]
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
There is a race condition issue between the IRQ context trying to
trigger preemption and the user context trying to submit commands to
the GPU. The check in a5xx_flush() API only updates the wptr if the GPU is
not in preemption. In the cases where we move from PREEMPT_START to
PREEMPT_NONE there is a small window where the preempt state is still
in START but the CPU context switches to the user thread which is in
the a5xx_flush() call to update the wptr, but fails to update the wptr to
the GPU since the preempt state is not PREEMPT_NONE. This leads to a
GPU stall.
Introduce a new intermediate state PREEMPT_ABORT and
change preempt_trigger() to use gpu's current ring instead of the
ring retrieved from get_next_ring() while in this state.
Change-Id: I333e9de19824bd373901bbc8afc829de04635017
CRs-Fixed: 2081164
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
This change is to move specific node parsing code to other place
for early splash feature on auto platform, not impacting kernel
booting process of other platforms.
Change-Id: I6deed1a75545c82ee777d9b4269f1420ab2eb07a
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
Free the IRQ in msm_gpu_cleanup. This is required
to avoid failures from devm_request_irq on subsequent
retries to load the GPU in case the previous attempt
failed somewhere after successful call to
devm_request_irq.
Change-Id: I90d98199a1d7867e3f7b51f8e2293fa28e4612fa
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
LK's pool is reserved for running on its code stack. So once
LK exits, the memory region it stays on should be released
and reused by system.
Change-Id: Iec5af69573eb633de48c931a052bd596f5ed3bda
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
When enabling animation/static splash in LK, drm/kms driver needs
to involve handoff code to support smooth transition. In display
driver's probe, it will do following items:
1. Check the status in LK for early splash.
2. Add data bus bandwidth voting in function sde_splash_init.
2. Handle SMMU mapping issue to avoid SMMU fault problem.
3. Bypass hardware reset to avoid glitch.
And after user's space is up, when first commit's vblank comes,
it will call functions to:
1. Tell LK to stop static/animation display and to exit.
2. Set early_domain_map_attr to 1 to enable stage 1 translation in
iommu driver.
3. Check the property of commit.If it's for HDMI, release HDMI
resource. If for DSI, release DSI resource.
4. Recycle the memory to be available to system.
5. Withdraw the bus bandwidth voting.
Change-Id: If425f044e2c40301eed57375a33a26ec1970abd5
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
On A5XX GPU hardware clock gating needs to be turned off before
reading certain GPU registers via AHB. Turn off HWCG before calling
adreno_show() to safely dump all the registers without a system hang.
Change-Id: Ic0dedbad550ab5d414cea7837672e586a7acd370
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Remember if the A5XX hardware clock gating is currently
enabled or disabled to avoid inadvertently enabling it.
Change-Id: Ic0dedbada3734a257ac966c041d06695f3521ad4
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Enabling and disabling the power at various points in the ->show()
call flow may have detrimental effects. For all targets make sure
power is on before reading any register and leave it on until we are
all done.
Change-Id: Ic0dedbad4d37a11634174105fc3ee6fe3713a143
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The generic msm_gpu_pm_resume/msm_gpu_pm_suspend functions have
built-in reference counting but the a5xx specific functions
are doing unconditional a5xx specific setup / teardown that
would behave very badly if they were not accompanied by an
actual power up / power down.
Change-Id: Ic0dedbad549c4ea9a5c68b0ca43eb98e0449d54b
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
drm_property_create prints WARN_ON while passing parameter
DRM_MODE_PROP_IMMUTABLE, so replace it with drm_property_create_range
Change-Id: I48e02125f751c29c94bf9f734bff84352359c001
Signed-off-by: Daocai.yang <c_daocai@qti.qualcomm.com>
Update vblank reference counts via the exposed sde_crtc_vblank
function, rather than attempting to zero it on the side during
CRTC disable operations. This allows the power voting to be
updated correctly based on the vblank reference count value.
CRs-Fixed: 2037677
Change-Id: I7026a1b239503a2b1d97ad7bb61fbc0a4a38d7ea
Signed-off-by: Clarence Ip <cip@codeaurora.org>
