Commit graph

578935 commits

Author SHA1 Message Date
Linux Build Service Account
5fd499075e Merge "ARM: dts: msm: Add VOL_UP node for MSMFALCON and interposer" 2016-12-09 19:59:08 -08:00
Linux Build Service Account
9743dc9288 Merge "ARM: dts: msm: Enable core hang detect feature on msmfalcon" 2016-12-09 19:59:07 -08:00
Linux Build Service Account
e9b171cb47 Merge "phy: qcom-ufs: Modify the vdd-phy min-max range" 2016-12-09 19:59:06 -08:00
Linux Build Service Account
a541a81870 Merge "ARM: dts: msm: Specify the WLED interrupts properly for pmi8998/pm2falcon" 2016-12-09 19:59:05 -08:00
Linux Build Service Account
250b1c4028 Merge "ARM: dts: msm: Add PM support for msmfalcon" 2016-12-09 19:59:04 -08:00
Linux Build Service Account
06a6328b57 Merge "ARM: dts: msm: Update clock mmss node for MSMfalcon/Triton" 2016-12-09 19:59:03 -08:00
Linux Build Service Account
98a2f941e2 Merge "msm-core: use get_user() API to read userspace data/settings" 2016-12-09 19:59:02 -08:00
Linux Build Service Account
301af28cab Merge "ARM: dts: msm: Modify QRD interposer dts file for msm8998" 2016-12-09 19:59:02 -08:00
Linux Build Service Account
3160351d53 Merge "ASoc: msm: Add changes to support multiple meta key value pairs" 2016-12-09 19:59:01 -08:00
Linux Build Service Account
65c54e155a Merge "iommu: io-pgtable-arm: Use correct bitmask for pgd entry" 2016-12-09 19:59:00 -08:00
Linux Build Service Account
fc284a8972 Merge "iommu: iommu-debug: Allow full dma_addr_t sized address for atos" 2016-12-09 19:58:59 -08:00
Hemant Kumar
bf2d967e5d ARM: dts: msm: Configure MPM for qusb2phy_dpse_hv for msm8998
In host mode upon XO shutdown high speed and full speed device
connection is not getting detected because mpm is not configured
to monitor for Dp line state change.

Change-Id: I34e3f586b99b6ff1af1d2323d4f272ee3cca7fa2
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2016-12-09 18:57:31 -08:00
Linus Torvalds
b40f046740 mm: remove gup_flags FOLL_WRITE games from __get_user_pages()
This is an ancient bug that was actually attempted to be fixed once
(badly) by me eleven years ago in commit 4ceb5db975 ("Fix
get_user_pages() race for write access") but that was then undone due to
problems on s390 by commit f33ea7f404 ("fix get_user_pages bug").

In the meantime, the s390 situation has long been fixed, and we can now
fix it by checking the pte_dirty() bit properly (and do it better).  The
s390 dirty bit was implemented in abf09bed3c ("s390/mm: implement
software dirty bits") which made it into v3.9.  Earlier kernels will
have to look at the page state itself.

Also, the VM has become more scalable, and what used a purely
theoretical race back then has become easier to trigger.

To fix it, we introduce a new internal FOLL_COW flag to mark the "yes,
we already did a COW" rather than play racy games with FOLL_WRITE that
is very fundamental, and then use the pte dirty flag to validate that
the FOLL_COW flag is still valid.

Change-Id: I42e448ecacad4781b460c4c989026307169ba1b5
Reported-and-tested-by: Phil "not Paul" Oester <kernel@linuxace.com>
Acked-by: Hugh Dickins <hughd@google.com>
Reviewed-by: Michal Hocko <mhocko@suse.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Kees Cook <keescook@chromium.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Willy Tarreau <w@1wt.eu>
Cc: Nick Piggin <npiggin@gmail.com>
Cc: Greg Thelen <gthelen@google.com>
Cc: stable@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Git-repo: https://chromium.googlesource.com/chromiumos/third_party/kernel.git
Git-commit: 19be0eaffa3ac7d8eb6784ad9bdbc7d67ed8e619
Signed-off-by: Dennis Cagle <d-cagle@codeaurora.org>
2016-12-09 17:43:44 -08:00
David Collins
e25600294b ARM: dts: msm: disable VDD_APC0/1 CPR aging adjustments on MSM8998v2
Disable VDD_APC0 and VDD_APC1 CPR aging measurement and
adjustments for all local CPR fusing revisions.  It is unknown
which future revision will have the initial aging sensor
difference fuse blown.  Software must not attempt to perform an
aging measurement unless this fuse is blown.  Therefore, disable
aging measurements on all future revisions.

Modify the open-loop and closed-loop voltage adjustments
accordingly so that the maximum 15 mV aging margin is present
for all CPR revisions.

Change-Id: I4546a7994fc0442bf82d36ca0a404a57be8c7dd3
CRs-Fixed: 1097587
Signed-off-by: David Collins <collinsd@codeaurora.org>
2016-12-09 15:58:42 -08:00
Subbaraman Narayanamurthy
7b232891df qpnp-fg-gen3: Use the correct property name to get fastcharge current
Currently GEN3 FG driver reads "qcom,nom-batt-capacity-mah"
property from the battery profile device node to use that for
notifying fastcharge current to the charger driver. Change that
to use "qcom,fastchg-current-ma" property which seems to be more
appropriate. Update all the battery profiles that are used with
GEN3 FG to follow that.

Change-Id: I119e6af297b37a06a227475f712f938367fb65bc
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
2016-12-09 15:33:59 -08:00
Subbaraman Narayanamurthy
688a4e14e1 ARM: dts: msm: rename battery profile used for msm8998 QRD
To match with other battery profiles used for GEN3 fuel gauge,
rename the battery profile used for msm8998 QRD platform.

Change-Id: I9a12ac11b6bd303eb32b4e03e116281bca664d06
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
2016-12-09 15:33:52 -08:00
Syed Rameez Mustafa
6e24ba90a2 sched: Ensure proper task migration when a CPU is isolated
migrate_tasks() migrates all tasks of a CPU by using pick_next_task().
This works in the hotplug case as we force migrate every single task
allowing pick_next_task() to return a new task on every loop iteration.
In the case of isolation, however, task migration is not guaranteed
which causes pick_next_task() to keep returning the same task over and
over again until we terminate the loop without having migrated all the
tasks that were supposed to migrated.

Fix the above problem by temporarily dequeuing tasks that are pinned
and marking them with TASK_ON_RQ_MIGRATING. This not only allows
pick_next_task() to properly walk the runqueue but also prevents any
migrations or changes in affinity for the dequeued tasks. Once we are
done with migrating all possible tasks, we re-enqueue all the dequeued
tasks.

While at it, ensure consistent ordering between task de-activation and
setting the TASK_ON_RQ_MIGRATING flag across all scheduling classes.

Change-Id: Id06151a8e34edab49ac76b4bffd50c132f0b792f
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
2016-12-09 14:30:41 -08:00
Olav Haugan
8cf404403a sched/core: Fix race condition in clearing hmp request
There is a race condition between clearing an HMP request for active
migration and the actual active migration. Active migration can he
half-way through doing the migration when the HMP request can be cleared
by another core. Move clearing of HMP request to the stopper thread to
avoid this.

Change-Id: I6d73b8f246ae3754ab60984af198333fd284ae16
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
2016-12-09 13:45:42 -08:00
Olav Haugan
584d38f189 sched/core: Prevent (user) space tasks from affining to isolated cpus
We don't want user space tasks to run on isolated cpus. If the affinity
mask that the user space task is trying to set only includes online
cpus that are isolated return error.

Also ensure that tasks do not get stuck on isolated cores. We are not
properly updating the mask that we check against the current CPU so we
might end up thinking we can run on the current CPU. Fix this.

Change-Id: I078d01e63860d1fc60fc96eb0c739c0f680ae983
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
2016-12-09 13:45:42 -08:00
Jack Pham
a3e98f0134 usb: phy: qmp: Select usb3 phy mode before initializing PHY
Make sure the USB3/DP PHY mode selection is switched back to
USB3 mode before proceeding with PHY initialization. This fixes
a bug when DisplayPort previously uses the PHY and does not
switch it back which causes the POWER_DOWN_CONTROL register write
to not take effect and results in USB3 PHY initialization failure.

Change-Id: Idad0f80eda6192ccae9e824f1f76c7071806ffec
Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-12-09 11:24:01 -08:00
Manaf Meethalavalappu Pallikunhi
c2ec16b9e1 power: bcl: Add frequency mitigation as an optional property for BCL
For targets with LMH DCVSh hardware and OSM, BCL software frequency
mitigation is not required. Since hardware is doing the frequency
mitigation, there is no need for the HLOS BCL frequency mitigation.
So make the properties "qcom,mitigation-freq-khz" and
"qcom,thermal-handle" as optional properties.

Change-Id: I0062f3b39f00ff2f0e74affcffbcf1afd89d3b2f
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
2016-12-09 19:48:33 +05:30
Manaf Meethalavalappu Pallikunhi
54fb4f8396 ARM: dts: msm: Add BCL peripheral configs for pmfalcon
Add pmfalcon BCL peripheral related configs to enable the BCL
peripheral driver. Add configs like vbat interrupt, ibat interrupt,
vbat polling delay, ibat polling delay, etc.

Change-Id: I9d7cc82c50c1b09610f5a4eac86af4617389f23f
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
2016-12-09 19:45:56 +05:30
Ashwanth Goli
d9db5fe079 defconfig: Enable config INET_DIAG_DESTROY
Enable config INET_DIAG_DESTROY for msm_falcon 32-bit

Change-Id: I39c5ac30070ff8555ed712a99796b9405717b072
Signed-off-by: Ashwanth Goli <ashwanth@codeaurora.org>
2016-12-09 18:06:01 +05:30
Amey Telawane
eae5dd568b ARM: dts: msm: add qdss node support for msmtriton
Add support to enable qdss components on
msmtriton. Reuse msmfalcon coresight nodes
for msmtriton.

CRs-fixed: 1094175
Change-Id: I34a3ad2da7f8e267f0d570c0329ac9b73a43309e
Signed-off-by: Amey Telawane <ameyt@codeaurora.org>
2016-12-09 17:48:03 +05:30
Gaurav Singhal
41b99b48c5 NFC: Inform CLF whenever eSE is powered off
When the eSE is powered off, the “system” needs to give
8ms to the capacitor connected on the SVDD line to discharge.

We should inform the FW we just powered off the eSE.

Change-Id: I864fd8f75ded6ab8c42ea36bcdadcdbe924e927d
Signed-off-by: Gaurav Singhal <gsinghal@codeaurora.org>
2016-12-09 15:43:21 +05:30
Taniya Das
151d532101 clk: qcom: Add support for debugfs measure clock
Introduce clk_debug_mux which would support clocks to be allowed to measure
clock frequency from debugfs.

Change-Id: I81c32a876b33f5a7773485a76897ff9cbed45a76
Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-12-09 15:04:41 +05:30
Vijayavardhan Vennapusa
61f63921e5 ARM: dts: msm: Add qcom,msm-imem-diag-dload node on msmfalcon/msmtriton
The diag dload memory region is part of IMEM. USB Diag driver
queries this device node for the memory address to access and update
USB PID and serial number. Hence add qcom,msm-imem-diag-dload node
on msmfalcon and msmtriton.

Change-Id: Ib283941037469833786b793c1e31e69e1c95d45d
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
2016-12-08 21:19:52 -08:00
Hemant Kumar
47b27b4d0f usb: qusb2: De-assert TCSR_QUSB2PHY_CLAMP_DIG_N_1P8 upon boot up
This prevents leakage on 1p8 power rail upon boot up when usb cable
is not connect.

Change-Id: I28a4f495293863361843eb30b2d20f1f57889f95
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2016-12-08 20:30:52 -08:00
Puja Gupta
02871aa947 ARM: dts: msm: Move boot_rom_ahb_clk to proxy voted for msm8998
Proxy vote for gcc_boot_rom_ahb_clk for modem pil on msm8998 instead
of keeping the vote until the modem was shutdown.

Change-Id: Ib32d40351179a687eca38228c4503e4a9a88c28d
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
2016-12-08 17:03:10 -08:00
Patrick Daly
149c51d5f2 iommu: arm-smmu: Fix clock reference count error
When an atomic iommu domain attaches, an additional vote for both
clk_prepare, bus_bw, and regulator_enable must be held. The prior logic
only did this if the atomic domain was the first to attach to the iommu.
Fix this.

As a side effect, add reference counting for bus_bandwidth voting such
that a call to arm_smmu_enable_clock() followed by
arm_smmu_disable_clocks() will not always result in a bus bandwidth
vote of zero.

Change-Id: I7f88ea845a281c8c1def4f642e61262b53b60e1a
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
2016-12-08 14:32:20 -08:00
Hemant Kumar
a8c976f55a usb: phy: qusb2: Add support to vote for regulator L2a
L2a is required to lock the phy PLL upon bus resume when
exiting from XO shutdown. This LDO powers REFGEN block
which is required to be powered on so that phy PLL gets
locked as part of wakeup from XO shutdown.

Change-Id: Ia0e3d574de7c78534832e4f8749672eb6fcde1f0
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2016-12-08 13:54:27 -08:00
Hemant Kumar
10957dd96e sound: usb: Handle implicit feedback data endpoint properly
For the devices supporting implicit feedback over data endpoint
usb audio driver instantiates snd_usb_endpoint as sync_endpoint
even though there is no real usb sync endpoint exists. QMI driver
looks for usb endpoint if sync_endpoint is instantiated and bails
out if endpoint related context does not exist. This causes such
devices to not work. Hence do not bail out if sync ep context
does not exist and continue preparing the QMI response.

Change-Id: I7d96555573cfd6cca1ca56c877d78fde943f8100
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2016-12-08 13:37:31 -08:00
Siddhartha Agrawal
355786d15d msm: mdss: dp: correctly ref count the pll resources
This fixes the issue where the dp pll resource was not correctly
keeping a refcount on the pll resource. This will fix the bootup
warning when both DSI and DP are enabled.

Crs-Fixed: 1088737
Change-Id: I19f8eef7f664a58cac1a082b8195e48c52613c5d
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
2016-12-08 12:37:08 -08:00
Osvaldo Banuelos
31a66f3234 clk: msm: clock-osm: don't use version register to enable WDOG status
The hardware version register does not return the expected
version value. The register is located in register space that is
accessible to the secure world only. This results in WDOG status
register not being enabled. Use the chip version instead.

CRs-Fixed: 1099112
Change-Id: I014c823bcf2545f005205dde326a074eaa5d7a6a
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
2016-12-08 11:59:14 -08:00
Shankar Ravi
cb5b41659b ARM: dts: msm: Update camera GPIO, VREG config for msmfalcon interposer
1. Update PMIC gpio configuration for
   front and rear camera.
2. Correct VANA GPIO.
3. Correct the CSID VREG Voting.

Change-Id: I1e72bf8855ea1150eb2cedaee82d04610b09bdae
Signed-off-by: Shankar Ravi <rshankar@codeaurora.org>
2016-12-08 15:28:40 +05:30
Vijayavardhan Vennapusa
e5b3bf88ce defconfig: msmfalcon: Enable audiosource gadget driver
Enable required audiosource driver that is required for audio
over accessory dock to work.

Change-Id: Ifeb779a3323c505d482eb53ad96a1b8aec0f3af5
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
2016-12-08 12:04:18 +05:30
Meng Wang
043b01d09a include: clock: remove ifdef from header file
As audio-ext-clk.h is finally included in device tree and
and using ifdef results in compilation failure. Delete
ifdef from audio-ext-clk.h.

CRs-Fixed: 1090500
Change-Id: Ib6f715c3f606770e7e0b1f0f84ab50e442398cd0
Signed-off-by: Meng Wang <mwang@codeaurora.org>
2016-12-07 22:24:56 -08:00
Ashay Jaiswal
9c6653b0b1 qpnp-fg-gen3: Add support for PMFALCON in Fuel Gauge
Add support of PMFALCON PMIC in FG driver. PMFALCON
FG core uses same SRAM map as PMI8998v2.0.
While at it, add workaround flag variable to keep track
of all hardware specific workarounds.

CRs-Fixed: 1096793
Change-Id: I8ba73276fd30f6eaf935ed77b75601f1322c0ba6
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
2016-12-08 11:16:15 +05:30
Nicholas Troast
d804378a31 smb138x-charger: enable the watchdog timer when parallel is enabled
If software becomes unresponsive then the battery could be overcharged by
the parallel charger. Enable the watchdog so that when the bite timer
expires then charging will be disabled by hardware.

Change-Id: I82febbc28c05563d052c6eed034adc817df39790
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
2016-12-07 15:22:57 -08:00
Nicholas Troast
5b55bcfa96 ARM: dts: msm: enable the watchdog bark interrupt for smb138x
The smb138x parallel charger device has a watchdog timer that will
disable parallel charging if it is not pet by software. Enable it.

Change-Id: Ie28323cdabccdc64196fae25deb2f56dfbb5a0e7
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
2016-12-07 15:22:49 -08:00
David Collins
4bf6721985 ARM: dts: msm: reduce VDD_GFX CPR max floor to ceiling range for MSM8998v2
Reduce the VDD_GFX CPR maximum floor to ceiling voltage range for
each corner in order to meet the most recent hardware guidelines.

Change-Id: Ie70a698fbed442e8826f0bc30c5ef6bdfd5b3e1f
CRs-Fixed: 1098577
Signed-off-by: David Collins <collinsd@codeaurora.org>
2016-12-07 14:41:29 -08:00
Shubhraprakash Das
b9a96eb2e5 msm: camera: isp: Ignore bus error from RDI write master
Bus error can be generated on RDI write master even if there
is no data sent on it. This is not actually an error hence
ignore it.

CRs-Fixed: 1098568
Change-Id: I8dc24f3c4926f008d114778c890ad2c2902f84b9
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
2016-12-07 13:52:00 -08:00
Shubhraprakash Das
f230f0f67b msm: camera: isp: Stop stats stream properly
When the camif input is disabled the stats streams need to be
turned off as well. Stop the stats stream by following the
correct stop sequence instead of just turning off the
stats write masters.

CRs-Fixed: 1098562
Change-Id: I4789bf9e837b1c0af7288e26ff02c4068638337a
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
2016-12-07 13:47:50 -08:00
Shubhraprakash Das
97587bf5cb msm: camera: isp: Add secure mode to isp
Add option to put the isp hardware in secure smmu mode. The
isp stats will still be in non secure mode. Add ioctl to
indicate which buffer queue will be in secure mode so that
they can be mapped in secure mode

CRs-Fixed: 1060631
Change-Id: Ibf2050d0814cc2aaf22a6f510847054d78fd7477
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
2016-12-07 13:46:20 -08:00
Shubhraprakash Das
757c94f42f msm: camera: isp: Initialize registers after reset
Initialize the qos registers and turn on interrupts after reset.

CRs-Fixed: 1089171
Change-Id: I8ed92a835fec1d5297448f440c19cc22ba52728b
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
2016-12-07 13:34:26 -08:00
Harshdeep Dhatt
ac782356a0 ARM: dts: msm: Specify coresight trace ID for msm8998
Specify the graphics coresight trace ID in the device tree
file.

Change-Id: I30a10a63b320cd3cb6d7cc4ef2fba423f697a66f
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2016-12-07 13:55:50 -07:00
Lokesh Batra
ac4034d803 ARM: dts: msm: Add GPU coresight properties for msm8998
Add properties in the GPU device tree for coresight. Define GPU
name and its funnel connections.

CR-fixed: 988516
Change-Id: Ibf2e369c2a4732ebc7471ee103bc8d5d934247ec
Signed-off-by: Lokesh Batra <lbatra@codeaurora.org>
2016-12-07 13:55:10 -07:00
David Collins
b3ce4f6026 ARM: dts: msm: disable VDD_GFX CPR aging adjustments on MSM8998v2
Disable VDD_GFX CPR aging measurement and adjustments for all
global CPR fusing revisions.  The initial aging sensor difference
fuse will not be blown on parts with revision 3 so software must
not attempt to perform an aging measurement on these parts.  It
is unknown which future revision will end up utilizing aging so
also disable aging measurements on all future revisions as well.

Modify the open-loop and closed-loop voltage adjustments
accordingly so that the maximum 15 mV aging margin is present
for all CPR revisions.

Change-Id: I4d413a2b3320d421c487aff1a97e72bd2678b19f
CRs-Fixed: 1097587
Signed-off-by: David Collins <collinsd@codeaurora.org>
2016-12-07 12:07:24 -08:00
Skylar Chang
38b489ccd4 msm: ipa3: check the rx_door_bell value on disable
In WDI2.0, seeing some issue about rdy_ring_rp_va
is not equal to rdy_comp_ring_wp_va because wlan-fw
still update the doorbell after ipa host-driver
issue the CH_DISABLE cmd to ipa-uc. The fix is
to compare rdy_comp_ring_wp_va and rx_door_bell
values instead.

Change-Id: Ibe57c7d5ba9e45260c12528910f173e347259d7c
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
2016-12-07 10:50:58 -08:00
Ram Chandrasekar
e219034e04 msm: thermal: Notify LMH DCVSh driver after freq mitigation request
LMH DCVSh hardware doesn't generate a debug interrupt, when HLOS
CPU frequency cap is the only throttling value coming to the hardware
aggregator logic. The LMH DCVSh requires atleast one of the hardware
algorithm to throttle to generate a debug interrupt. So there will be
a case where, LMH DCVS driver won't notify scheduler about the
throttling frequency if HLOS is the only reason for throttling.

LMH DCVSh driver now exposes a new API, to trigger the frequency polling
loop. KTM is updated to use this API to trigger the LMH DCVSh polling,
whenever there is a new software frequency cap. This will ensure that
the LMH DCVSh will notify the scheduler even if software is the only
throttling reason.

Change-Id: I92b1bd9a5efc9810eea721b088dff1bd6eef3838
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2016-12-07 11:36:37 -07:00