dwc3 core IRQ's depth (disable depth) is going out of sync due to
disabling it from dwc3's state machine when there are multiple
time USB composition switch is being performed before USB cable
connect. Linux IRQ framework doesn't decrement disable depth
count with enable_irq() when IRQ is enabled previously but it does
increment disable depth every time disable_irq() is called. This
results into dwc3 core IRQ to remain disable causing USB enumeration
failure as unknown device due to USB controller driver is not
seeing any of RESET and CONNECT DONE interrupt although USB controller
has posted those events into event buffer. Fix this issue by
making sure that USB core IRQ is disabled by default, and
enable/disable it from dwc3 suspend/resume only.
Change-Id: I665b15f6b5aca7d63e9ced29ec94b09524ae91be
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
request_irq() for dwc irq is called in dwc3_gadget_start()
when msm-dwc3 is in suspended state because usb cable is not
connected. dwc3 resume happens upon USB connect, it enables
already enabled irq. This result into unbalanced enable irq
warning. Fix this by moving request_irq to dwc3_probe().
CRs-Fixed: 999124
Change-Id: I61ec085778fe43b87de18a84829ea3f5280c451c
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
commit 55b8e041e6 ("sched: take into account of limited CPU min
and max frequencies") has introduced a typedef bug and is fixed
in this change.
CRs-Fixed: 1006303
Change-Id: I6f75d4d0179a79544b4180a3ba155916c861edb5
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Hardware does not require pad bytes in egress packets when uplink
aggregation is not enabled.
CRs-Fixed: 1002396
Change-Id: I86459b7bc18da16b66f6c701ac324f28be8848fa
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Print format %p displays the kernel address while bypassing the
kptr_restrict sysctl settings.
Change the print format for addresses from %p to %pK. If
kptr_restrict is enabled, addresses are printed as zeroes. To view
the actual addresses, disable kptr_restrict by -
echo 0 > /proc/sys/kernel/kptr_restrict
CRs-Fixed: 987054
Change-Id: Icb8ef62c8263ae7b17d6883c0e6a1c93d2156a6a
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Add lineptr interrupt support by making use of INTR_PROG_LINE
register part of the interfaces. This would generate the interrupt
when the configured pixel location in the panel video timing in terms
of video raster structure is reached for the frame. The lineptr can
be updated through the lineptr_value node. Any modification to the value
would take effect immediately for video mode panels.
Write a value from 1 to [line size] to enable interrupts, 0 to disable:
/sys/devices/virtual/graphics/fb0/lineptr_value
To handle interrupt, read from:
/sys/devices/virtual/graphics/fb0/lineptr_event
Change-Id: I33c09b2dcfc7b49ce94f5e31b5b297b0445fd073
Acked-by: Mike Mager <mikemager@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
A DSI fifo error can occur on one DSI controller and HW will
not generate the mdp done isr interrupt for both controllers
in case of pp split and dual dsi. Current dsi reset routine
only resets the busy checks for the controller where errors
are reported. It should reset both controllers because HW
is not going to the isr for other interrupt where fifo error
is not reported.
Change-Id: I4de587aec0b54d942637fbea3cbe13cb2bdac893
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change parses and populates PPB control and config register
offsets separately. Its not necessary every ping pong blocks
to have both control and config registers.
Change-Id: I4be0dcaa9fabbd81e4875255d808707bf1e97e8e
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
This change enhances the existing MDP ISR routine handlers
to handle multiple MDP register sets. Maintain IRQ
handlers and callbacks in a single file.
Change-Id: Iea6e77be1eaab5ccf2fd89f7c98e2dd328af7de0
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Default bpp for destination format is set if mixer type
for WB is MIXER_TYPE_WRITEBACK. Ensure that correct bpp
is fetched from format type.
Change-Id: Iff7cf58363a83e9a4999115382c5551110104ead
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
when mapping the MDP framebuffer, driver needs to aggregate all
buffer length from each sg node.
CRs-Fixed: 996243
Change-Id: Ia4825e96b2e12f2328c9cc3197051f5e47c4daff
Signed-off-by: Camus Wong <camusw@codeaurora.org>
In some cases, updating fps need both porch and clock
update. Add support to update both porch and clock settings
for a given resolution to attain required fps.
Change-Id: I8c75ef09121c2d20e04380ead2b805c7b114acad
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Starting sde 3.0, driver needs to use uncompressed
bandwidth calculation for the ib bandwidth vote.
Add support to use this calculation and enable
it for sde 3.0.
Change-Id: I6a7ba7573a67a52bddb4881415217d7401c97cf3
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Mdp clock needs extra calculations when qseed3
is enabled. Update mdp clock calculations accordingly.
Change-Id: Id488793e9bb6aa7a2578af828f31d1d2b27d51e5
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Adjust the maximum sdm bandwidth limits for msmcobalt.
Change-Id: I269e805465200ef1aa76476110946ee89d432cbd
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Update bandwidth vote calculation for video mode
panels to account for the amortized prefill.
Change-Id: I2a62b0fbd15e678b21329184a5edc0502c33b413
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Starting with sde 3.0, prefill bandwidth can
be amortized depending on the configuration.
This change adds support for this feature.
Change-Id: I501e11325365ec900a2ef8ee5bcbcd66f5647f64
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Add support for DMA multirect pipes available in new MDP revision.
These pipes are able to fetch two different buffers and rectangles to
allow more layers to be fetched. Add support and proper validation
checks for limitations.
CRs-Fixed: 987777
Change-Id: I588ecd7829a45908241f6d9fa1e97147e79798f6
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Enable MPP4 by default at boot-up which enables HDMI 5V.
This is needed for continuous splash screen to make sure
5V is not turned off when booting into kernel.
Change-Id: Ibbce17bb85d82cca42c0bcf0f53fadecace103fb
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
MSM mdss 3xx hardware supports destination scaling for upscaling the
layer mixer output to the panel resolution. This change adds the new
interface to support the user space client using this feature.
CRs-Fixed: 988990
Change-Id: Ie267f0fd81cd8cf04a5c1f1c6a8c48d456a3035e
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
Current resolution switch calculation is using the wrong
values for the fps calculation.
Correct the values, by using the correct pixel clock
value and adjusting if dsc is enabled as well as
use the default fps, for panels where default frame
rate is not 60.
Change-Id: I4be0a9d5d163b0630e8cfeb930e72c32f487ccb1
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Add support for dynamic fps up to three decimal values for
hdmi. The new fps is provided in multiple of 1000. eg. for
60 fps, 60000 is provided and for 59.94fps, 59940 is provided.
Change-Id: Ib16bf546721ba204f8a47733327e7be77b76b821
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Add mdss_rotator node with smmu subnodes.
Change mdss_mdp to interrupt controller so rotator can
receive interrupt routed by mdp handler.
CRs-Fixed: 972831
Change-Id: I5e0f8f06897ff0d4b55aa1f9fc8114dd02451649
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Change adds separate rotator to capabilities if the platform
supports, so that user space can update its configuration.
Change-Id: If3a1b0f41eaa912a30c20c4c188a896c7bc1efe4
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Perform revision initialization as soon as possible in order to have
all capabilities that depend on revision read from hardware
enumerated by the time we start parsing and doing other
initialization.
CRs-Fixed: 987777
Change-Id: Ide1fa99b876a3347a4e46c11261a9e7a32b8f47a
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
The MDP control path mutex takes care of synchronizing display
suspend path and ESD thread to avoid race conditions. The DSI
OFF path is also taken care of under the MDP control path mutex.
Hence, avoid the usage of DSI ctrl mutex in ESD thread.
Change-Id: I523130bac65f9c4b736e19eb5888c83b9542ed27
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Panels can support different dsc revisions based on the scr.
Add scr revision support for dsc based on updated spec.
Change-Id: Icbd93ed592a7d79dcd7f72b52d73572ced384759
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
V3 version of mdss dither block has been moved from dspp to
ppb. Based on mdss revision the driver should enable the dither block in
dspp/ppb. Change enables driver to handle dither block in ppb.
Change-Id: Iaa11755b46417db1e2a12cb2f2b6028cd7530c0b
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: Ping Li <pingli@codeaurora.org>
Smmu context fault handler provides the fault iova
information but does not provide any information about
xin client. This patch registers the context fault
handler in MDSS software to get the vmid/xin client
information. It also dumps the registers for source
associated with respective vmid client
Change-Id: I2a833a4b5e81e36f4d7af23a3968c9755424b7a7
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Update the panel reset sequence and panel ON/OFF command delays
for truly 1080p command mode and video mode panels. This will
help to reduce the suspend/resume latencies related to display
for this panel.
Change-Id: I503ce32546483a6eac79c41b581486e7a3ae8735
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Truly 1080p panels need one frame update before updating the
backlight. Add this post init parameter to truly panel nodes
Change-Id: Icd495a5a98a068b5c47c9c25dfa3c0bda676c6f0
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Program MPM_CONFIG bit 0 to release reset to Adrastea before
executing cold boot.
CRs-Fixed: 986579
Change-Id: Ic9605be675c10ea2973e57ea5aae0e8ee2f893f2
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
Include audio external clock header file instead of platform
specific header file in audio-ext-clk driver to remove the
platform dependency as the same driver is used across multiple
platforms.
CRs-fixed: 1006637
Change-Id: Ib51007d544c240fd17c058dcb133f12e7bf2c5d7
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
SMD channel can get into OPENED state before even the G-Link channel
gets into OPENED/CONNECTED state. This can cause the SMD channel events
to get dropped.
Synchronize handling the SMD_OPEN_EVENT & subsequent events in an SMD
channel with the G-Link channel open operation.
CRs-Fixed: 997404
Change-Id: I4c44011b7fa3b59cbe70a125735e04a076c4d3ca
Signed-off-by: Dhoat Harpal <hdhoat@codeaurora.org>
The current GRO implementation relies on NET_RX to complete
processing or the max possible TCP segment size for it to flush the
GRO coalesced packets. This leads to coalescing a large number of
packets which translates to very few ACKs. Since the number of
ACKs are very few and delayed during the slow start phase (stretch
ACK's), we see that the initial throughput ramp up is slow compared
to normal RFC TCP where we send an ACK per two packets. Note that
there is no difference between GRO and non GRO after the max window
size is reached.
Add a mechanism within rmnet_data to force the flush of packets
every 10 micro seconds (experimentally determined) by default. This
is controlled by the module parameter "gro_flush_time" and can be
configured to any value less than a second. To disable this feature,
set this entry to 0.
This reduces the coalesce of packets which translates to increased
number of ACK's compared to normal GRO but lesser ACK's compared
to NO GRO. There is no increase in power for a day to day use case.
Note that this optimization is specific to TCP GRO path only.
Some useful stats below for TCP DL at 400Mbps -
|TCP GRO Default | TCP GRO flush timer 10us
==================================================================
iperf 1st second tput | 300Mbps | 330Mbps
coalesce ratio | 15 | 4.5
CRs-Fixed: 961186
Change-Id: Ie8d76c493d61f3f4c256dbaa0378b22a361eed49
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
In order to guarantee stable operation some parts may require
elevated voltages when operating at LowSVS or SVS corners. Thus,
increase the VDD_APC0 and VDD_APC1 CPR ceiling voltages for the
LowSVS and SVS corners to match the Nominal ceiling voltage.
Change-Id: I4e50943923aabae104c8d2c8f512b28693132bbb
CRs-Fixed: 1008621
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Dynamic OT is applied before rotator operation to control QoS.
Since REGDMA cannot access QoS registers directly, rotator
driver needs to wait for rotator idle before changing any
OT settings. Once new OT is applied, REGDMA can resume
queueing until OT changes again.
CRs-Fixed: 989206
Change-Id: I2fd07a957b0d8414c855fafcff7a2613695efff0
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
This patch upgrades v4l2 rotator driver to be compatible with the
latest v4l2 framework.
CRs-Fixed: 972831
Change-Id: Iddbaaceaeba6cee5c7935077f4a92a0361fa8c75
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Actual CPU's min and max frequencies can be limited by hardware
components while governor's not aware of. Provide an API for them to
notify for scheduler to be able to notice accurate currently
operating frequency boundaries which helps better task placement
decision.
CRs-fixed: 1006303
Change-Id: I608f5fa8b0baff8d9e998731dcddec59c9073d20
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
At present scheduler calculates task's demand with the task's execution
time weighted over CPU frequency. The CPU frequency is given by
governor's CPU frequency transition notification. Such notification
may not be available.
Provide an API for CPU clock driver to register callback functions so
in order for scheduler to access CPU's cycle counter to estimate CPU's
frequency without notification. At time point scheduler assumes the
cycle counter increases always even when cluster is idle which might
not be true. This will be fixed by subsequent change for more accurate
I/O wait time accounting.
CRs-fixed: 1006303
Change-Id: I93b187efd7bc225db80da0184683694f5ab99738
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
dm_crypt required to support full disk encryption.
Change-Id: I990fb3317b4c19ad9b1c8c114a5bbc3faf208ff8
Signed-off-by: Harshal Trivedi <htrivedi@codeaurora.org>
The OSM device needs access to the APCS common register space
to configure the LMh RCG which serves as clock source to OSM.
Add this register space to the OSM device.
Change-Id: I493e711463e2458abe735d440f98fbc80b11c208
CRs-Fixed: 1007896
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
