When there is a fatal error on ADSP, audio subsystem restart(SSR)
gets triggered. As a part of audio SSR, trigger codec DSP
SSR to reset the codec DSP state.
Change-Id: Id9cbda04a4c36070e52919d3a34ebc871ac22a8e
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
When there is a fatal error on ADSP, audio subsystem becomes
unresponsive. Add support for audio subsystem restart that
helps to recover ADSP and codec from the crash without
rebooting the entire system.
CRs-Fixed: 1069188
Change-Id: I2939e9fd37e96f37101b93dabd86cfdaaf06907f
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
MBHC mechanical detection, electrical detection and micbias
registers are not getting updated in hardware after subsystem
restart results in no IRQ during headset plug insertion.
Set these MBHC registers to volatile for headset plug
detection to work properly.
Change-Id: Iaec3a17e5eed952ba0abdcffbf321ad942486769
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
Modify the sleep state settings for BLSP1 UART3 pins to optimize power
when the usecase isn't in play.
Change-Id: I1405a8561b1ecb2e3da87ed8b26fb087433a1c11
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Add debug statistics for GSI commands in order to
improve debug capabilities
Change-Id: Iee80fd2bf4b549665a12791009f0cf5ecc7653b9
CRs-Fixed: 1079245
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
The hardware frequency that LMH DCVSh hardware has requested may not
match an actual frequency of CPU. The OSM hardware will aggregate and
match this request to a nearest frequency mentioned in the clock plan.
The current lmh dcvs driver exposes this request without matching to
a frequency value in the OPP table.
In order to reflect the final mitigated frequency, match the mitigation
frequency request from LMH DCVSh to a nearest CPU frequency floor
in OPP table.
Change-Id: Iffc380898eac33f6c30c3808eb38d7bb499f5769
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
The LMH DCVS hardware along with different monitoring algorithms, also
provides support for HLOS to vote for a CPU mitigation request. The
hardware will aggregate this request and will place the aggregated
mitigation request to OSM. The generic CPU cooling device doesn't take
advantage of this platform CPU mitigation feature.
Register the LMH DCVSh device as a platform cpu cooling device. When
registered, thermal CPU cooling device will place the mitigation request
with the LMH DCVSh hardware bypassing the cpufreq software. This will
allow faster mitigation action.
Also, thermal core framework exposes standard sysfs interfaces for
querying the cooling device state. Using this sysfs interface, users
can query the instantaneous CPU frequency mitigation request from
LMH DCVSh hardware.
Change-Id: I23762895d04dd6f1da8bb496f2a4cf22c1b34216
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
cpu device can be controlled by a hardware platform device and in those
cases the cpu cooling device interface should communicate with the
platform device instead of the cpufreq module.
Allow platform drivers to register with CPU cooling with their frequency
mitigation functions. This allows the cpu cooling interface to
communicate the frequency mitigations to the platform driver directly.
Change-Id: I47960b002bf1bce1cd588de2892de46793a95562
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
The adc notification callback assumes that it will end up selecting
the correct state. However, if the parameters are outside the
expected values, the code could end up dereferencing a null pointer.
Fix this by returning before that pointer is dereferenced.
Change-Id: I42642b475a1032c3a7395336381f3bd6c1396dde
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Reported by static analysis tools. generic_device_group() may return
NULL on an error case.
Change-Id: I33e8e859e99d4f7c4616aeee1da8214497e30625
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Update the VDD_APC0 and VDD_APC1 CPR RO scaling factors
for msmcobalt v2 to match the latest hardware characterization
guidelines.
CRs-Fixed: 1080409
Change-Id: I8250304e918f55d233e9b3f01c57f297f73e74ba
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Handle WDSP_EVENT_PRE_SHUTDOWN event to indicate link down event to G-Link
core and the clients of G-Link. Handle WDSP_EVENT_POST_BOOTUP event to
indicate link up event.
CRs-Fixed: 1080354
Change-Id: I12c04ceb7af51cc5d2f0c79b524ef783dc5f749e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Add sysfs entry for force fw_update support in Goodix
driver.
Change the usage of kstrtoul to sscanf in driver to avoid
portability issues.
Change-Id: I147a3e465170dda7af415ade29c04257d9b11a6b
Signed-off-by: Shantanu Jain <shjain@codeaurora.org>
Add debugfs entries for address and data to read the registers
of Goodix controller.
Change-Id: I6543d523e39771615d0e1b684780141e108a2aa4
Signed-off-by: Shantanu Jain <shjain@codeaurora.org>
The MDSS DP driver has compilation issues on msmfalcon 32-bit builds.
Remove config for the driver to skip compilation till the relevant
issues are resolved.
Change-Id: I8b4d464c793fd943abca2b9041f5751abc9ed22b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msmcobalt QVR has different hardware design with MTP.
Add sound card entry for msmcobalt QVR to enable wsa,
earpiece and microphones.
CRs-Fixed: 1078551
Change-Id: Ic55c44de74e537463a218619861f28c1e6eb66c1
Signed-off-by: Meng Wang <mwang@codeaurora.org>
If the bootloader uses the long descriptor format and jumps to
kernel decompressor code, TTBCR may not be in a right state.
Before enabling the MMU, it is required to clear the TTBCR.PD0
field to use TTBR0 for translation table walks.
The commit dbece45894 ("ARM: 7501/1: decompressor:
reset ttbcr for VMSA ARMv7 cores") does the reset of TTBCR.N, but
doesn't consider all the bits for the size of TTBCR.N.
Clear TTBCR.PD0 field and reset all the three bits of TTBCR.N to
indicate the use of TTBR0 and the correct base address width.
Change-Id: Ib497ef7ecdee6c517205ec76724283d4cbd89bdc
Fixes: dbece45894 ("ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores")
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-commit: 117e5e9c4cfcb7628f08de074fbfefec1bb678b7
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
The GPU PLL initial configuration is modified to 800MHz and also update the
RCG to be able to support force enable/disable for gfx3d_clk_src.
Change-Id: I8e6d7dba762b678070d66e291347af2cdf804ae5
Signed-off-by: Taniya Das <tdas@codeaurora.org>
