Initialize maximum number of zorder's programmable by the client
to 4 for msm8992 target.
Change-Id: I090ddf709322c91fd40e9403ad7471d87c5e82af
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Use target specific ping pong buffer register offsets instead
of hard coded ones to program control and config parameters.
Change-Id: Id446452d6ff42e886b8e3232a1143c1b0a742489
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
[imaund@codeaurora.org: Resolved context conflicts]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
This change adds support to autorefresh the command mode panels
without having to manually issue a kickoff. We need to enable
sys/class/graphics/fb0/msm_cmd_autorefresh_en to configure after
how many idle ticks(read ptr/vsync) should we trigger a frame.
e.g. If we want to send an update at 60fps
we need to echo 1 > sys/class/graphics/fb0/msm_cmd_autorefresh_en
to disable we need to echo 0 >
sys/class/graphics/fb0/msm_cmd_autorefresh_en
Change-Id: Ib0cda1142f8fadfa6cad5e61e0c7fb36fe43aca1
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
[imaund@codeaurora.org: Updated INIT_COMPLETION call to
reinit_completion]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
The new sequence is intended to improve pll locking time. This patch
is part of new sequence for phy ctrl in DSI driver side.
Change-Id: I9c38d98f1e32cfa1e5f4d12156a6fa9cb15e3049
[veeras@codeaurora.org: Done as part of 3.18 upgrade
Removed msm8994-mdss.dtsi changes from this commit]
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Both in dual dsi and single dsi case, only dsi0's phy regulators
need to be programmed. Reduce the dependency between the two
dsi's for enabling and disabling the dsi0's phy regulators.
Add dsi0's phy regulator base to both dsi's as it can
independently program it, if the panel is boot with dsi1 or dsi0.
Change-Id: I04bfa4025fb5e20e3624577275d01b37a9f723bf
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
[imaund@codeaurora.org: Removed changes to files that do not exist
in msm-3.14]
[veeras@codeaurora.org: Done as part of 3.18 upgrade
Removed apq8084-mdss.dtsi, msm8226-mdss.dtsi, msm8916-mdss.dtsi,
msm8939-mdss.dtsi, msm8992-mdss.dtsi, msm8994-mdss.dtsi
changes from this commit]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
Function mdss_mdp_ctl_perf_get_transaction_status tracks mdp
status whether a commit is currently in progress. If it is
then we don't schedule the work queue, otherwise schedule it.
Cases where work queue is not scheduled, waitforpp takes care
of notify frame done. In case of last frame update, work
queue takes care of notify frame done.
Change-Id: I98c9af4ec412f06d48e0ae57e5973bf34be9110d
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Add debugfs nodes to enable and configure fbc
for simulation panels.
Change-Id: Ie469f10ff6285fa4778357505d0b973ba677e38e
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
[cip@codeaurora.org: Use debugfs_create_u32 for u32 variables]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
When there are any issues halting pipes during free, we go into recovery
sequence where pipes that cannot be cleaned up are forcefully staged to
get recovered. After this we need to remove them to complete recovery
sequence, otherwise it will remain active which is not the intention.
Also add check to ensure we catch such cases for all dual mixer cases.
Change-Id: If9fb04130de286eb1bf9a8171461df693dc2493d
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
There is possibility that the time of mdp flush bit set
and the time of dsi flush bit are cross vsync boundary.
Therefore wait4vsync is needed to guarantee both flush
bits are set within same vsync period regardless of mdp
revision.
CRs-Fixed: 766349
Change-Id: I5fd1b7c94f119d8e5f1fdd2ceb5476ed27a730fc
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Add maximum bandwidth per pipe, maximum mdp clock rate
and mdp clock fudge factor to the capabilities exposed
to the display driver user space.
Change-Id: I3266bcaf7df8caa127cbeebc8430e7b3a6e3ecf7
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Horizontal scalar support on VIG pipe was only intended for 8092. Since
there is no need to support this chipset, this change will revert all
HSCL functionality to remove any confusion.
This reverts commit 13f08126290f40aae7476bfe8c374459f0fcd041.
Change-Id: Ia14b89faed2a3285b5ef5af6d16ebf225ffa4cda
Signed-off-by: Benet Clark <benetc@codeaurora.org>
IGC(Inverse gamma correction) feature is supported on source side pipes
in MDP. Clients of MDP driver can enable the feature using overlay ioctl
interface. Change adds support for clients of driver to enable the
feature.
Change-Id: I5243b001acffff869f9369211fd724d7dd75e8a1
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
For source pipes post processing feature params are cached in the pipe
structure. Post processing(pp) feature versions can change across
different versions of mdp and might require changes to caching code.
Post processing driver can handle caching the params based on version.
This change moves the caching into post processing driver
Change-Id: Ic02fec43dbbff5d4404b618d6d82b2c8b8eef07a
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Updated the HDMI driver to conform to new 2.0 specification. Updated EDID
parser to handle new data blocks defined in CEA-861-F and added support for
yuv420 output format type.
Change-Id: Ia424c13c585e7f3a9b572a472a997c13aa7e3c0f
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
User-space decides how many layers to send for MDP composition using
max blending stage value passed by the driver. Currently driver sends
this value based on its internal enum value which does not reflect the
correct number of blending stages that HW supports. So user-space makes
independent assumption to derive at correct value by deducting 2. This
is incorrect design and may lead to unforeseen issues. Fix it by sending
correct max blending stage value.
Change-Id: Iaaed7b6824e6ef445ca202fb993d1061811b5ce0
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Starting MDSS 1.5, display controller can blend 7 layers excluding
base layer. If a pipe is staged on stage6, it requires use of extension
register. Current logic has a bug where if VIG3 of RGB3 pipes are on
stage6 then configuration is incorrect and leads to bad HW behaviour.
Fix this by correcting the staging logic.
Change-Id: I4f34783a9bd8ae5e0898bcf25755cf687f195211
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
MDP block supports picture adjustment feature on the DSPP which can be
enabled/disabled by driver clients. Change adds the support in post
processing driver and allows clients of driver to configure the PA block
in DSPP.
Change-Id: I22e3df32fd67fda4029eeb4740ad47917ae7e3a1
Signed-off-by: Benet Clark <benetc@codeaurora.org>
The PP cache currently stores the 'data' structure for PAv2. For newer
MDP targets, the PP res cache needs to store the PAv2 config data
structure, which has some PAv2 configuration info as well as the 'data'
structure nested inside. The configuration structure is needed in the
cache because it contains info for newer targets required when updating
the registers.
Change-Id: Idd1aa23687245ab7cc71c2c7a9cb74958c77dcec
Signed-off-by: Benet Clark <benetc@codeaurora.org>
At cmd_stop, spin lock protection is necessary when reset rdptr_enabled
to 1. Otherwise race condition may happen and cause timeout.
CRs-Fixed: 766216
Change-Id: I128f73a069d3068c852f4b25c6515ec834e82162
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Rotator is a non real time client. Limiting the read and
write transactions can help preventing peaks in the bandwidth
required by the rotator client.
Change-Id: I479706598827236daa82a7f42924ecafd37724b8
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
While using simulator panels through debugfs, all the necessary
parameters are updated except panel_max_vtotal. This parameter is used
to derive bandwidth and mdp clock rate for video mode panels. So if this
parameter is not updated while switching simulator panel from low to high
resolution then we are under voting and under clocking MDP. This leads to
under-runs. Fix this by updating panel_max_vtotal with latest v_total.
Change-Id: Ia51340c597e8234d59660b43f19a841ffb96dad3
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Default the pinctrl state to NULL before selecting
a pinctrl state. This ensures that IS_ERR_OR_NULL
called on the variable will return true.
Change-Id: I3e798cade45f4ef4179b1883e2eb33c3fd7d851f
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
MDP block supports histogram feature in DSPPs which can be enabled
or disabled by driver clients. This change adds the support in
post-processing driver to allow histogram configuration in DSPPs.
Change-Id: Ib8cdf83f557c1a44304bc168187ca826486cdc3d
Signed-off-by: Ping Li <pingli@codeaurora.org>
Add systrace events to log the time to process a blank
request; this helps to profile the time that display
driver takes during the power transitions.
Change-Id: I0081c3825a4776561db248123d701c25101e9245
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
In order to successfully halt vbif client, need to ensure that client
core clock is on while halting and waiting acknowledge of vbif halt.
Change-Id: I9f17e90f34cf4b3033bc4f3b23e2c1df8fc3aa69
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
While refactoring VBIF registers programming
(commit 41efd125ffe5403698155043073dd826abc534cf)
software reset programming was switched from using
mdp based to vbif base, this is incorrect programming
and software reset wouldn't work in case hardware
behaves incorrectly.
Change-Id: I8738bc4fc96ec8ba7130a891231c34bd4ce10449
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Reading the default panic LUTs after disabling the splash clks in mdp
probe when continuous splash is disabled in lk causes the crash. This
change disables the splash clks after reading the panic LUTs.
Change-Id: I8fc4ed0f515a3b657a40cd430150353ffb90db35
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Reduce vsync waiting time only when vsync is still enabled.
Otherwise, it will trigger waiting for next vsync mistakenly
and timeout eventually.
CRs-Fixed: 762791
Change-Id: Ic3df12a4b449fa6d6cbbd1169e890b0cf3f67db1
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Frame buffer memory could still be fetched until panel is completely
blanked, in order to avoid potential page faults by unmapping early,
move unmapping of this memory until after panel is blanked.
CRs-Fixed: 763046
Change-Id: Ib7eea73a7549b453cf2fc31a31f5cc3e9e1cce39
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
During high performance scenarios, sometimes the DSI RDBK registers
are not getting cleared. This can cause improper read return values
since the RDBK data count will not get reset in such cases. Add
memory barriers during reset of RDBK registers to ensure that
the registers are cleared.
Change-Id: I870744b58c3e4064ca9f04f92e831d69139336db
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
The use of bl_lock is to protect backlight related resources, however by
holding it during display thread shutdown it may lead to deadlock if the
same is being acquired inside display thread. Reduce the scope of the
lock to just the backlight resources to prevent deadlock.
Change-Id: I6e4b9a970c4a5a050caab1b3714e90eda107edee
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
MDSS HW can support different variants of split modes and each one
is unique based on specific needs. Refactor current implementation
such that terminology for each split is easily understood. Along with
this, enable single DSI split layer mixer configuration which can be
used to save power because it reduces MDP's core clock. Following
are the currently supported split modes.
* split_none: single ctl with single lm and single display interface.
i.e. 1080p/720p single dsi, single lm config.
* dual_lm_single_display: single ctl with split lm and single display
interface. i.e. WQXGA eDP or 4K HDMI or 1080p single dsi, split lm.
* dual_lm_dual_display: synchronized dual ctl with dual lm and dual
display interfaces. i.e. WQXGA dual-DSI or 4K dual-DSI
* pingpong_split_dual_display: single ctl path with single lm but two
synchronized display interfaces. Split is done after pingpong HW
module. i.e WQXGA dual-dsi on msm8939/msm8992 etc.
Change-Id: I3edcc0c056cc2a1a76a819f0892035a10730118d
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Currently notify frame is done in wait4pingpong, and there
may not be a real need for the pp_done_work workqueue. But
we still keep it because to trigger the notification once
the last frame sent to display is actually transferred.
So, cancel the workqueue if singalling is already done
within the wait4pp but keep the work queue for the idle
cases. This can avoid unnecessary CPU scheduling in a lot
of cases.
Change-Id: I2099f18e48502fe7d0eac337f04d8e3f4711c2f2
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
When shutting down, notify userspace that panel state has changed.
So that it can change its state accordingly.
CRs-Fixed: 756363
Change-Id: I2b1c36742918350609b7cab83e7ad58e65db036c
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Rotator release all is called in cases such as shutdown or display going
down. In these cases need to release all rotator resources, in current
logic doesn't release all resources and ends up freeing session twice.
Refactor release logic to ensure rotator resources are cleaned up.
Change-Id: I453dfed96a6ee01328480737a5b619f67960360a
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
In case of failures during overlay kickoff, ctl may be destroyed.
Need to ensure we check for availability before dereferencing.
Change-Id: I32ead416ac10467b5bf1085d959794078f870db5
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
If rotator work is scheduled, and a new rotator configuration comes
before it starts running, it may pick the new configuration which may
no longer match. In order to avoid mismatch between configuration and
buffer programmed, flush the pending work before reconfiguring it.
CRs-Fixed: 756253
Change-Id: I0e5683522810cf39cc4c4f4cd0224ee6f79c06ce
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
While continuous splash screen is in progress need to ensure that other
display devices such as HDMI don't come in and modify state of clocks
and votes before handoff completed.
Change-Id: Ia85c4805b38080adecc5025affea37c392b11071
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Block all post processing and histogram IOCTLs if partial update sysfs node
value is set to true, except for the disabling calls.
Change-Id: Ib32a668747569d9ad898f5519d7fd22b9bb41547
Signed-off-by: Ping Li <pingli@codeaurora.org>
Create a sysfs node for partial update state. This dyn_pu sysfs node will
be used to show whether partial update feature is enabled or not,
so the we can dynamically enable/disable post processing features
accordingly.
Change-Id: I7012e7830575942299ae07c956eb27244e622365
Signed-off-by: Ping Li <pingli@codeaurora.org>
On msm8994, implement the overflow recovery sequence
for all overflow interrupts. For other targets,
implement the overflow recovery sequence only
when the clock lane is not present in stop state.
Change-Id: If47e5cfe95a2caa204daf2ea4bae55af4a1713f9
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add NULL checks and array bounds checks to ensure
that no dereferencing of invalid data occurs in
the MHL driver.
Change-Id: I855412b4603cbe416d901be88a24a28dc6770d2c
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Due to HW problem, when BWC is enabled, panic is asserted continuously
as long as pipe with BWC decode is fetching from the memory. This
continuous panic assertion causes unnecessary CPU throttling and causes
lot of side effects. To prevent the issues related to HW problem, disable
BWC on video mode panels on msm8994. On CMD mode panels, use BWC but
disable panic signal as long as there is no video mode secondary display.
It is user-space's responsibility to not use BWC when primary display is
CMD mode but any kind of secondary video mode display is active.
Change-Id: Idb219e61599d2e2564bd4076fcfc787cd99c8d4d
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
[mattw@codeaurora.org: resolved a trivial context conflict in mdss.h]
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Currently ppp engine adds huge fudge factors for bandwidth
calculations. Remove the fudge and add right bw requirement
calculations for the same.
Change-Id: I798d2bf6ac4c4cff13c82efdd53e5c73fa84b1ff
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
At present, the DSI error interrupt is cleared before the
respective errors are handled. This might cause re-generation
of the error interrupt which causes the ISR to be scheduled
again. Hence clear the DSI error interrupt after the errors
are handled.
Change-Id: I42b1d0beee8597e60b4103106ebbeffe6caf065e
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
To enable/disable a particular interrupt mask for DSI, we currently
read the DSI_INT_CTRL register and add/remove the interrupt mask on
top of the current register value. With this approach, we sometimes
clear some interrupts without handling them. Handle this case by
writing back only the required interrupt mask bits to the
DSI_INT_CTRL register.
Below is an instance of such issue when a DSI register read
operation is performed.
<3>[ 342.509070] mdss_dsi_isr: ndx=0 isr=3200002
-> At first, DSI error interrupt is received.
<3>[ 342.512239] mdss_dsi_err_intr_ctrl: intr=1310003 enable=0
-> During DSI_INT_CTRL read/write operation,
we clear the CMD_DMA_DONE interrupt which arrives few milli
seconds after DSI error interrupt.
<3>[ 342.517620] mdss_dsi_fifo_status: status=44441000
<3>[ 342.522351] mdss_dsi_timeout_status: status=1
<3>[ 342.526980] mdss_dsi_err_intr_ctrl: intr=3210002 enable=1
<3>[ 342.693365] mdss_dsi_cmds_rx: failed to tx cmd = 0xa
-> This causes a CMD DMA timeout even though the
CMD_DMA_DONE interrupt arrived.
Change-Id: I82ba142d4da4ae5f4a1a2761c32b8af7964b538b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Add DFPS horizontal front porch support in addition to
vertical front porch. It adjust horizontal front porches
as needed to achieve specified new frame rate.
Change-Id: I05bccc4f515ba45a39642171799117584ae057ad
(cherry picked from commit 842c510f0759426535112d14a72a1c7658f430bd)
[veeras@codeaurora.org: Done as part of 3.18 upgrade
Removed msm8939-cdp.dtsi, msm8939-mtp.dtsi, msm8939-qrd-skuk.dtsi
from this commit]
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Generate the HDMI resolution id names based on resolution timing
details. This makes the code generic for all resolutions.
Change-Id: I097f450f5a85c85c1e81b7c7b1351d9c7228ba01
(cherry picked from commit 0e21977a89c126d610763c8ed9baf013bc9fa72a)
[veeras@codeaurora.org: Done as part of 3.18 upgrade
Removed msm8994-fluid.dtsi, msm8994-pinctrl.dtsi from this commit]
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Define a new low power state for display (LP2), in which the panel is
on but cannot accept any updates. Add support for transitions in and
out of this new power state.
Change-Id: Ie25ec157bf6bb16efb76d535822c2e978a0bc2e1
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Releasing file node after process node causes the kernel
panic because process node is already freed. Correct order
to release nodes should be file node followed by process node
when PM API fails.
CRs-fixed: 753912
Change-Id: I252fc9eabaf0ba81d19b1989b03100849cdeca38
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
