Modify ACD_EXTINT_CFG so that ACD calibrates every time OSM toggles
full freq signal. This is recommended by hardware guidelines to
prevent ACD from mitigating when CPU clock frequency is boosted.
CRs-Fixed: 1088429
Change-Id: I07856ea8b332dbf12654fdd0b5d5518355f1c350
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add mem-acc threshold and crossover voltage properties to the
VDD_APC0/1 CPR devices and a matching mem-acc crossover voltage
to the OSM device. Update the APM threshold voltage
to 800 mV for both clusters.
CRs-Fixed: 1088429
Change-Id: I747fd7665401803998b2824ace6dedbc5797b17f
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support for configuring the highest memory accelerator
(MEM ACC) threshold voltage. This threshold voltage is used at
runtime to determine which CPRh virtual corner to program into
the OSM sequencer registers in place of the fixed MEM ACC
configuration specified in the OSM LUT.
CRs-Fixed: 1088429
Change-Id: Ida29eaca139c1ddd6439d11a8bd51526366f2a34
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for configuring the memory accelerator (MEM ACC)
threshold voltage and the MEM ACC crossover voltage.
The threshold voltage is used to restrict the floor to ceiling
voltage range of all corners so that they cannot cross the
the MEM ACC threshold voltage due to CPR operation. The
crossover voltage is set when switching the MEM ACC
configuration.
If specified, the APM and MEM ACC crossover voltages are added
to the array of corners after all true corners. If both are
specified, then the APM crossover corner is added before the MEM
ACC crossover corner (i.e. last corner = MEM ACC crossover and
second to last corner = APM crossover).
CRs-Fixed: 1088429
Change-Id: I2b9b746071579ba9d4bcdcfb6cb755ca08a73182
Signed-off-by: David Collins <collinsd@codeaurora.org>
Grabbing the mutex should not be done from netlink_sock_destruct() but
from netlink_release()
CRs-Fixed: 1094434
Change-Id: I69ae0d8589a0878b9758619893848afc272179c5
Signed-off-by: Eric Dumazet <edumazet@google.com>
Patch-mainline: linux-netdev @ 11/26/16, 04:54
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
We want a generic way to insert an RCU grace period before socket
freeing for cases where RCU_SLAB_DESTROY_BY_RCU is adding too
much overhead.
SLAB_DESTROY_BY_RCU strict rules force us to take a reference
on the socket sk_refcnt, and it is a performance problem for UDP
encapsulation, or TCP synflood behavior, as many CPUs might
attempt the atomic operations on a shared sk_refcnt
UDP sockets and TCP listeners can set SOCK_RCU_FREE so that their
lookup can use traditional RCU rules, without refcount changes.
They can set the flag only once hashed and visible by other cpus.
CRs-Fixed: 1094434
Change-Id: Ib4967b801cc5b48c8ac4793b7a03fbfafba2234a
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Tom Herbert <tom@herbertland.com>
Tested-by: Tom Herbert <tom@herbertland.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Git-commit: a4298e4522d687a79af8f8fbb7eca68399ab2d81
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[subashab@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
Add support for addtional performance cluster speed bins. Speed bin
fuse 2 and 3 devices can run with a quad core CPU fmax of 2.361 GHz and
single core CPU fmax of 2.457 GHz.
CRs-Fixed: 1086294
Change-Id: I08c3b8bc7e4d40c80be588f05b9439b339f46afc
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the VDD_APC0 and VDD_APC1 CPR devices to support two additional
speed bins. This allows CPR operation on bin 2 and 3 parts which have
different performance cluster frequency configurations compared to bin
0 and 1.
CRs-Fixed: 1086294
Change-Id: Id0854f1094ee3e4d4b1961f98a77003f7bcca1da
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The OSM LUT may have duplicate frequencies between one
and four core count compatible frequencies. If the selected
frequency exists for both single and quad core, select the quad
core frequency by default. Also, expose only 4-core frequencies
and the absolute maximum frequency to clock consumers.
CRs-Fixed: 1086294
Change-Id: I2424bfdfd381241d307862113451082a9727a903
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The values written into OSM sequencer registers #55 to #58
correspond to indexes into the CPRh virtual corner table not
indexes into the OSM table. Correct this.
Change-Id: I02baca9a410f08c82c34fe82925c0ead22111e5b
CRs-Fixed: 1086294
Signed-off-by: David Collins <collinsd@codeaurora.org>
The maximum VDD_APC1 voltage has been increased to 1.136 V
for msm8998 v2. Update the AVS limits of L2 SAW and the
CPR aging reference voltage to reflect this.
CRs-Fixed: 1086294
Change-Id: I863bee32e1e66d9656fc70748628b25606b59e47
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Support a total of 32 fuse combos to cater to MSM8998
parts blown with speed-bins 2 and 3.
CRs-Fixed: 1086294
Change-Id: Id03a418f66c9cbb51c2be6904f682d15e82f78c8
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the VDD_APC0/1 max floor to ceiling range as well
as the open-loop and closed-loop Nominal fuse corner
adjustments to match the latest hardware characterization.
CRs-Fixed: 1086294
Change-Id: I920175ab16d5a3fc5cd3f117bba3fd1d37db3c5d
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add the necessary configuration to the OSM clock device in
msm8998 v2 to initialize ACD.
Change-Id: Ibdb861a50ad654be34e14e2bcc012fdf5063acaf
CRs-Fixed: 1053383
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Perform a complete or adequate check of return codes for several
functions, including __qseecom_enable_clk, ion_do_cache_op and
ion_sg_table(), used by qseecom.
Change-Id: Ib1682bdc6d3034a22586af62a3d8986c54d369d5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Add the demo battery profile to support 6A charging with pmi8998
on msm8998 MTP.
Change-Id: Id76ebe4a2591664d44d8003730f70defcb2899bc
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Clone the ascent battery profile to create a demo battery
profile to support 6A charging with pmi8998.
Change-Id: I57d33cadbe26d5298ef7149a004d14102d62f365
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Auto recharge happens when the charging is complete and the
battery SOC or voltage had dropped below certain threshold.
Along with having an option to configure recharge SOC threshold,
a way to configure recharge voltage threshold is required. Add
it. By default, charger is configured to resume charging only
based on the signal from FG based on battery voltage.
Change-Id: I0cd6ca6679c19bbdf4ad980a22d9976396028316
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Clearing the hmp request can cause a task to be freed. When a task is
freed the free call might wake up a kworker which will cause a
spinlock lockup (rq lock). Fix this by avoiding calling put_task_struct
when holding the rq lock.
In addition move call to clear_hmp_request out of stopper thread context
since it is not necessary to do this on the cpu being isolated.
Change-Id: Ie577db4701a88849560df385869ff7cf73695a05
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
In function edge_name_to_ctx_create, NULL check is missing after
kzalloc for edge_ctx variable.
NULL check validation is added.
CRs-Fixed: 1086686
Change-Id: Icbffbd9d02df97bda531353c41a7025b95a53991
Signed-off-by: Dhoat Harpal <hdhoat@codeaurora.org>
Allow clients of common clock framework to be able to use the
clock_debug_print_enable API.
Change-Id: Ia8e69dca8c0b84e4daf8ff1f4fb902d11435db76
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The clock nodes require the regulator nodes to be updated for interposer,
so add the same. Also update the gfx rail regulator phandle.
Change-Id: I08580f4eb04660cd1d123065976ba9bfec61b7d8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add the new perf configuration for msmfalcon and msmtriton.
Update the msmfalcon_defconfig also.
Change-Id: I8c3be2d0235395a338b758e4dc27a4b243bff62d
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
Add property to support multiple sensor which are same slave address
and used in the one platform.
Change-Id: Id6e648ecffd07de1fdafb6fc6187dc14e3e6e36e
Signed-off-by: Wei Ding <weiding@codeaurora.org>
Add entries for 88.2kHZ, 176.4kHz and 352.8kHz to supported
sample list for USB RX and TX backend.
Change-Id: I78261addaa84d1239b92e1528e77bbfcaa09105f
Signed-off-by: Ashish Jain <ashishj@codeaurora.org>
The critical clock handling in __clk_core_init isn't taking the enable lock
before calling clk_core_enable, which in turns triggers the warning in the
lockdep_assert_held call in that function when lockep is enabled.
Add the calls to clk_enable_lock/unlock to make sure it doesn't happen.
Fixes: 32b9b1096186 ("clk: Allow clocks to be marked as CRITICAL")
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit ef56b79b66faeeb0dc14213d3cc9e0534a960dee)
Git-commit: ef56b79b66faeeb0dc14213d3cc9e0534a960dee
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Change-Id: Ifefcbe4741ddd046755ecc24c3f2d619566c2823
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This call matches clocks which have been marked as critical in DT
and sets the appropriate flag. These flags can then be used to
mark the clock core flags appropriately prior to registration.
Legacy bindings requiring this feature must add the clock-critical
property to their binding descriptions, as it is not a part of
common-clock binding.
Cc: devicetree@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1455225554-13267-4-git-send-email-mturquette@baylibre.com
(cherry picked from commit d56f8994b6fb928f59481fabc25bcd1c2f9bd06d)
[tdas@codeaurora.org: resolve trivial conflict]
Git-commit: d56f8994b6fb928f59481fabc25bcd1c2f9bd06d
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Change-Id: I2bf824bd2446ca87baabd31c166119d6c5c90643
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1455225554-13267-3-git-send-email-mturquette@baylibre.com
(cherry picked from commit 2e20fbf592621b2c2aeddd82e0fa3dad053cce03)
Git-commit: 2e20fbf592621b2c2aeddd82e0fa3dad053cce03
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Change-Id: I88418dd25f356402219d7ff36ce791370c69114a
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Critical clocks are those which must not be gated, else undefined
or catastrophic failure would occur. Here we have chosen to
ensure the prepare/enable counts are correctly incremented, so as
not to confuse users with enabled clocks with no visible users.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1455225554-13267-2-git-send-email-mturquette@baylibre.com
(cherry picked from commit 32b9b10961860860268961d9aad0c56a73018c37)
[tdas@codeaurora.org: resolve trivial merge conflict]
Git-commit: 32b9b10961860860268961d9aad0c56a73018c37
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Change-Id: I003abf22da8600dd90ef397d293544b4bc9e0160
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Fix some potential issues in HDMI driver such as suspicious
dereference of NULL pointer and variable reference without
initialization.
CRs-Fixed: 1091211
Change-Id: I81a99bcc4201ccd72de1f812e9c4da36d6a81958
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Add sysfs and ioctl to adjust HDMI clock rate by certain PPM.
This function is required by clock recovery in broadcast in
which HDMI PLL should be adjusted in order to reduce the clock
drift in broadcast.
CRs-Fixed: 1086894
Change-Id: I1df15dd6aec44ae3e78bd4f80dc70d0d04760687
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Add bluetooth device tree node for WCN3990 chip in msm8998 QRD
VR1 board. Configure necessary power supply and clocks to enable
bluetooth.
CRs-Fixed: 1080773
Change-Id: I47b042dc79145a13142c02b0ef8da777efff3a8d
Signed-off-by: zhenchao <zhenchao@codeaurora.org>
Add bluetooth device tree node for WCN3990 chip in msm8998 QRD
SKUK board. Configure necessary power supply and clocks to enable
bluetooth.
CRs-Fixed: 1080773
Change-Id: I433c349ddfd6d83629080afadc6fbf79c3b8c635
Signed-off-by: zhenchao <zhenchao@codeaurora.org>
Add msm-core device to run power and temperature calculation
on the cores.
Change-Id: I3e8300f15757739714579055985e3fff1a4d8f86
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Before adding the irq affinity based qos request to the list, if
the affinity of the interrupt changes it will trigger notify call.
This notifier call will try to update the qos request. Accessing
the qos request which is not yet added to the list leads to a
NULL pointer exception.
Avoid this race by registering the notifier after adding the
qos request.
Change-Id: I99869cc233573b5db10e4f3224d65c29511050ea
Signed-off-by: Anil Kumar Mamidala <amami@codeaurora.org>
