Add new voter clocks of camss_jpeg0 clocks which are required by camera
client. Update the clock indexes for multimedia clocks for the same. Also
update the clock ops for hardware control branch clocks.
Change-Id: I4bc6608789b8b900e0af007d2ca24ba19f675cb7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add new bus master id to identify the pimem bus master
for bandwidth aggregation and QoS programming done
by the bus driver.
Change-Id: I0991065984b35511c33ab4c9bd274ad465d19601
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Model and configure MDSS DSI PLL using upstream clock framework
APIs. Add changes to define and register vco, divider, mux clcoks
as per common clock infrastructure.
Change-Id: Idc51070e2bb36d1a757d2714d2875a99901321a7
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
In order to avoid leakage between the graphics and the CX
rails, set the GPU_DD_WRAP_CTRL__GFX_PDN bit.
Change-Id: I7b2e59606e73c467c2b862f0162a176611d7ae3d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
As audio-ext-clk.h is finally included in device tree and
and using ifdef results in compilation failure. Delete
ifdef from audio-ext-clk.h.
CRs-Fixed: 1090500
Change-Id: Ib6f715c3f606770e7e0b1f0f84ab50e442398cd0
Signed-off-by: Meng Wang <mwang@codeaurora.org>
Update the code name from msmcobalt to msm8998. As a result, update
the filename containing "cobalt" and files content containing "cobalt".
CRs-Fixed: 1070840
Change-Id: I2c7b95e3e2a2fec7730724da9eeb86a39a77faf1
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Signed-off-by: Kyle Yan <kyan@codeaurora.org>
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Add support for the multimedia clock controller found on MSMFalcon
based devices. This should allow most clocks for multimedia peripherals
which includes display, video, camera etc.
Change-Id: If8aa0b094af5ff82fe66c95e3ef2f13632950d2e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add clock of_idx entries for audio external clock registered
to the qcom clock framework.
Change-Id: Ie592d06d2e09c2e263a2e9485a42eafb368e49cc
Signed-off-by: Meng Wang <mwang@codeaurora.org>
The gcc_gpu_bimc_gfx_src_clk and gcc_gpu_snoc_dvm_gfx_clk need
to left at their default state of ON. Remove controlling them
from the linux clock driver to avoid disabling them during
late_init.
Change-Id: If3d964840362b6147ba7c9e26c4a3f5d20e5a557
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The turing hlos1 and hlos2 vote clocks is required to be enabled before
accessing the turing SMMUs, so add support for the same.
Change-Id: I9e4b0d7cc5f164b207a1a0e2c1ae24bdfd8fa063
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The post vco divider clock in the DSI PLL can only be configured
to a fixed value of 1 or 4. Current implementation can result in
the divider being set to any value between 1 and 4 which can
result in failures while enabling the DSI pixel clock. Fix this
by replacing the post vco divider with a fixed /1 and /4 dividers
followed by a mux clock.
CRs-Fixed: 1064277
Change-Id: I01bc7304e446c622849c678c64a3fd6881413e89
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add support for the graphics clock controller found on MSMFalcon based
devices. This should allow graphics clocks for GFX clients to be able to do
clock functionality.
Change-Id: I753b40d574a4afc2104a5c2bfe64b4831fbce8a0
Signed-off-by: Taniya Das <tdas@codeaurora.org>
For MSMfalcon and MSMtriton, clock consumers requires dummy
rpmcc, gcc, mmss and gfx clocks for their operation so add
the support for registering dummy clocks as follows:
- Add clock-output-names property for the rpmcc, gcc, mmss
and gfx clock controller nodes.
- Add reset-cells property for clock controller nodes.
- Add two fixed clock nodes named as xo_board and sleep_clk.
- Remove RPM clock IDs from qcom,gcc-msmfalcon.h.
- Modify RPM clock names as per qcom,rpmcc.h file.
Change-Id: I06262fe271ab6ba81d4fa5f67315fd1b54edee8c
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Add support for the global clock controller found on MSMFalcon
based devices. This should allow most clocks for peripherals other than
multimedia clocks.
Change-Id: I1ec6309f32c658177580cc0601083d32bcdfad20
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Update the rpm-smd communication API to send across votes for clock
enable/disable to RPM. Use the clk_hw list for the RPM clocks and also
update the clock ids and clock names for RPM clocks.
Change-Id: I37ae97f22b1b39d040bb78c90b1ff231bc348fe6
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Introduce new master/slave ids to identify
the corresponding master/slaves for the
bandwidth aggregation done by the bus driver.
Change-Id: Ibed309284b47ba3f22ccbac45c750f3e366ec40e
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Remove the RPM controlled clocks and add missing clocks.
Also clean up clock flags and parent info for few clocks.
Change-Id: I7ae55f992be29a28617070ca7792f912592c3628
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Add support to measure the perf and power cluster clocks
via the debug mux on MSMCOBALT.
CRs-Fixed: 1059153
Change-Id: I1682481dfe22deef300ea9bd1db558ae634c9129
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add property "qcom,dtest-buffer" to specify which dtest rail to feed
when the pin is configured as a digital input.
Change-Id: I05b253147677ca66d926eaeaa680bd09e31247a5
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
for LV and MV subtypes.
Change-Id: I7bcf4347adce6ba9892d2e57a413d407d35fbc26
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Add support for controlling the hw_ctl bit of the
gcc_aggre1_ufs_axi_clk CBCR.
Change-Id: I856f2c76c3149f3704c47e6f8b0019805a1a0cd4
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
Update the Display-Port PHY and PLL configuration
with the recommended settings. Remove the
support for 9.72Ghz VCO frequency. Update the divider
settings to support the new frequency plan.
Update the Phy Aux settings and voltage/pre-emphasis
settings according to recommended configuration.
Change-Id: Ic4d206da3dc6b45214e7601e7556cfb0bef81a7d
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add separate voter clocks for controlling the mmss_camss_jpeg0_clk
from two clients on MSMCOBALT.
CRs-Fixed: 1049594
Change-Id: I530e35054fd512574bca9e5937317099f58d2bb6
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The wcss clocks are not owned by APCS, and thus should not
be modelled in the clock driver.
CRs-Fixed: 1054449
Change-Id: I7677bef6a58c028876b72dbade37c1064b428ee2
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
Add the block reset clocks which will be used by clients to
assert/deassert these clocks using the reset controller framework.
Change-Id: I19f4f6e764ffde26ecf3b7cce3fb53a9bf2cc91a
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add the new clocks and update the clock ids for GCC, GPU, MMSS clock
controllers. Also add the RPM clocks which are supported and would be
used by the clients for all clock operations for RPM controlled clocks.
There are separate MMSS and GPU clock controllers, so add the dummy
controllers for the same.
Change-Id: I5a98b6128f5d54163ab5d03c4c023a748e6a4e95
Signed-off-by: Taniya Das <tdas@codeaurora.org>
GPLL0 input to the multimedia and graphics clock controllers can
be managed by use of voting registers. Enable this usage and turn
off the inputs when no clocks within these clock controllers need
a GPLL0/GPLL0 divider input.
CRs-Fixed: 1009689
Change-Id: Iea17649eb63522510cf7887a630d17a2f64a615b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Update the graphics and multimedia clock frequencies and FMAXes
to align with the v2 and vq frequency plans. While doing so,
remove support for the gpu_pll1 PLL since it is not going to be
used to generate any frequencies.
CRs-Fixed: 1051170
Change-Id: I4d6547d95bd76d8ca6f4d729009d8b4a78716d5b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add the block reset clocks which will be used by clients to
assert/deassert these clocks using the reset controller framework.
Change-Id: I3e9f7f85bf1faf0e1bb501196ba9d7e197111a03
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The gcc_usb_phy_cfg_ahb2phy_clk clock will be managed by RPM.
There is no need to model it in the linux clock driver or to
control it from the USB driver.
Change-Id: I05641c2d532ada36623da1e1cc687c90bc4ee906
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
