Add support for configuring the memory accelerator (MEM ACC)
threshold voltage and the MEM ACC crossover voltage.
The threshold voltage is used to restrict the floor to ceiling
voltage range of all corners so that they cannot cross the
the MEM ACC threshold voltage due to CPR operation. The
crossover voltage is set when switching the MEM ACC
configuration.
If specified, the APM and MEM ACC crossover voltages are added
to the array of corners after all true corners. If both are
specified, then the APM crossover corner is added before the MEM
ACC crossover corner (i.e. last corner = MEM ACC crossover and
second to last corner = APM crossover).
CRs-Fixed: 1088429
Change-Id: I2b9b746071579ba9d4bcdcfb6cb755ca08a73182
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for addtional performance cluster speed bins. Speed bin
fuse 2 and 3 devices can run with a quad core CPU fmax of 2.361 GHz and
single core CPU fmax of 2.457 GHz.
CRs-Fixed: 1086294
Change-Id: I08c3b8bc7e4d40c80be588f05b9439b339f46afc
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the VDD_APC0 and VDD_APC1 CPR devices to support two additional
speed bins. This allows CPR operation on bin 2 and 3 parts which have
different performance cluster frequency configurations compared to bin
0 and 1.
CRs-Fixed: 1086294
Change-Id: Id0854f1094ee3e4d4b1961f98a77003f7bcca1da
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The OSM LUT may have duplicate frequencies between one
and four core count compatible frequencies. If the selected
frequency exists for both single and quad core, select the quad
core frequency by default. Also, expose only 4-core frequencies
and the absolute maximum frequency to clock consumers.
CRs-Fixed: 1086294
Change-Id: I2424bfdfd381241d307862113451082a9727a903
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The values written into OSM sequencer registers #55 to #58
correspond to indexes into the CPRh virtual corner table not
indexes into the OSM table. Correct this.
Change-Id: I02baca9a410f08c82c34fe82925c0ead22111e5b
CRs-Fixed: 1086294
Signed-off-by: David Collins <collinsd@codeaurora.org>
The maximum VDD_APC1 voltage has been increased to 1.136 V
for msm8998 v2. Update the AVS limits of L2 SAW and the
CPR aging reference voltage to reflect this.
CRs-Fixed: 1086294
Change-Id: I863bee32e1e66d9656fc70748628b25606b59e47
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Support a total of 32 fuse combos to cater to MSM8998
parts blown with speed-bins 2 and 3.
CRs-Fixed: 1086294
Change-Id: Id03a418f66c9cbb51c2be6904f682d15e82f78c8
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the VDD_APC0/1 max floor to ceiling range as well
as the open-loop and closed-loop Nominal fuse corner
adjustments to match the latest hardware characterization.
CRs-Fixed: 1086294
Change-Id: I920175ab16d5a3fc5cd3f117bba3fd1d37db3c5d
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add the necessary configuration to the OSM clock device in
msm8998 v2 to initialize ACD.
Change-Id: Ibdb861a50ad654be34e14e2bcc012fdf5063acaf
CRs-Fixed: 1053383
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
scm_call2 is printing the input arguments if TZ ret value is < 0
leading to information leak. Remove printing input arguments.
Change-Id: I21dd6d83fa979aed2c79ebb2c9c8de63a247dded
CRs-Fixed: 1076407
Signed-off-by: Swetha Chikkaboraiah <schikk@codeaurora.org>
Signed-off-by: Paresh Purabhiya <ppurab@codeaurora.org>
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
In existing HDMI PLL driver the VCO frequency value is truncated
so following PLL calculation could be impacted. Use 64 bit value
instead to maintain the necessary precision.
CRs-Fixed: 1086894
Change-Id: Iec3f65942dd152b0b7aa32af1a90039fff06cb34
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Clock recovery and dynamic resolution change require changing
HDMI clock rate while HDMI PLL is on. There are two paths while
clock is changed, one is atomic update which doesn't require
PLL tear down, the other is when clock rate change is too big
and a full PLL tear down is needed.
CRs-Fixed: 1086894
Change-Id: Ia202e0aee09f506a7bbe4e13702f30dee119ce8e
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Addition of Ngid breaks some third party applications, which
are dependent on a particular order of fields. This change
moves the field to the end, to fix this issue.
Change-Id: Ifdc781aca49dcb535d5fa5005b85dc87604560dc
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
