The MSM SDHCI controller defines the usage of 0xF in data
timeout counter register (0x2E) which is actually a reserved
bit as per specification. This would result in maximum of
5.3 secs timeout value. For some buggy SD cards, the core
layer wants to set the data timeout to 3 secs and on our MSM
SDHCI if we configure data timeout counter value to 0xE,
then we would get only 2.67 secs. Observed data timeout errors
for CMD25 on SDR104 card. Hence program data timeout counter to
0xF, to achieve at least 3 secs timeout value.
CRs-fixed: 470661
Change-Id: Ie1e192eb9c38ca3922bb1f518073a8ff0cb57f0c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
If preset value (bit 15) is enabled in sdhci host control2
register (0x3E), then the preset value registers(0x6F-0x60)
would be used for some of the settings such as clock and
drive strength. These are HW initialized registers and are
not properly initialized by MSM SDHCI controller. This is
resulting in low throughput for some of the modes such as
DDR50/SDR50. Hence, do not enable it for MSM SDHCI.
CRs-fixed: 474518
Change-Id: Iee1241355d14e6bcebc66c3a43abf1ec94d869c3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Ignore data timeout error for R1B commands as there will be no
data associated and the busy timeout value for these commands
could be lager than the maximum timeout value that controller
can handle.
CRs-fixed: 473435
Change-Id: I61f7463cf09648ad9fab83437abf5004effc7758
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This helps check the controller timeout logic in case of data
timeout errors.
Change-Id: Ia30757192e49865698c5f52940e1dc5d97746185
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The driver is using wrong clock rate to calculate the required
bandwidth and due to this voting is happening for more bandwidth
than it is required. This is ultimately preventing system core
voltage from entering into low power mode.
The sdhci_host clock indicates the clock rate as requested by MMC
core layer and the actual rate that is set is indicated by clk_rate
within struct sdhci_msm_host. As of now, sdhci_host clock is being
used to calculate the bandwidth whereas bus-bw-vectors-bps indicates
only supported bandwidths and hence a mismatch. Fix this by using the
right clock rate which is clk_rate within struct sdhci_msm_host.
Change-Id: If7d81e44a9b479c4c8e9fbaa7e092af2afb9cb9f
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This patch fixes the following issues in sdhci driver
from msm 3.9 kernel -
1. gpio_get_value_cansleep() is used from atomic context
resulting in warning from gpio driver. Move it to non-atomic
context.
2. Move sdhci_enable_preset_value() in set_ios callback after
clocks are enabled otherwise it would result in access to SDHCI
registers if clocks are disabled due to clock gating or suspend.
Change-Id: I231aa6e5c02669cf1aa3f21764642fa7da9a01ff
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The SDHC core power control IRQ gets triggered when -
* there is a state change in power control bit (bit 0)
of SDHCI_POWER_CONTROL register.
* there is a state change in 1.8V enable bit (bit 3) of
SDHCI_HOST_CONTROL2 register.
* Bit 1 of SDHCI_SOFTWARE_RESET is set.
This patch addresses the following 2 issues -
The reset state of 1.8V enable bit in SDHCI_HOST_CONTROL2 is 0
which indicates 3.3V IO voltage. So, when MMC core layer tries to
set it to 3.3V before card detection, the IRQ doesn't get
triggered as there is no state change in this bit. Hence, with
the current code, the VDD IO voltage is never getting set to
3.3V. This patch fixes this issue by setting the VDD IO voltage
to 3.3V whenever SDHC gets powered up.
We get different IRQ ACK status for each of these requests -
power on, power off, IO high, IO low. As of now, the driver is
not considering the IRQ ACK for IO high and IO low requests and
is returing prematurely from check_power_status() based on the
previous ACK for power on/off requests. This is resulting voltage
switch errors during voltage switch sequence for SD/eMMC cards.
This issue is fixed by passing the request type to
check_power_status host op so that driver can wait for its
corresponding ACK from power IRQ.
Change-Id: I07707ac5df731a0d3e4abead28076f0bbbf75c0a
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
MSM SDHCI doesn't control power as specified by the Standard
Host Controller 3.0 spec. Writing to power control register/
reset register/voltage bit of host control register would
trigger an IRQ with appropriate status bits set. Hence, use
host op check_power_status after writing to power control
register to check the status and wait until the IRQ is handled.
Change-Id: Ied1a82e385547f7f5d60807fc896ea5a13084657
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: fix trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict
& compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The SDHCi driver by default specifies a parameter that causes the
core layer to calculate a max discard value which will be set on the
mmc queue. Unfortunately the value calculated because of this would
be very small compared to what comes in by default. As a result of
this, any secure discard kind of operations are very slow.
Instead add quirk so that any SDHCi hosts that would like to use
the default value can do so.
Change-Id: Ifa1343c3e7f14b031da30b06203a8831ba544889
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
[venkatg@codeaurora.org: change max_discard_to was renamed to
max_busy_timeout in 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This patch checks the device state before starting a request.
It also prints out useful information in case of error
conditions.
Change-Id: Iaf87bb069c3ffb13c9b3f174c07c25d612bdcee9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: remove pm related stuff]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The BKOPS feature is supported for eMMC cards of version 4.41 and higher.
The BKOPS feature is one time programmable and once it was enabled on
a certain MMC card is cannot be disabled.
LA builds are often being used to verify phones that are targeted for
other HLOSes. Since not all the HLOSes implement the BKOPS features,
enabling this feature by default can cause instability when the phone
will be used by HLOSes other than LA.
Change-Id: I7b9eab0d04a86dfeaf7565dcda8bc9d2035fe02d
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add support to disable available SDHC slots at bootup controlled via a
module param with a bit mask of slots to disable. QDSS is one use case
where SDHC slot is disabled for trace output.
Example Usage:
Passing sdhci_msm.disable_slots=1 as kernel command line argument would
disable SDHC slot 1, whereas passing sdhci_msm.disable_slots=3 would
disable both slots 1 and 2.
Change-Id: I97bc517adfe4a1a81a97a2789d77404b0f22b124
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Add support for enabling clock scaling feature and indicate
the same to MMC core layer by setting the capability
MMC_CAP2_CLK_SCALE.
Change-Id: I24f144d3f727160c302966888fb439b3a39a0dde
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: sdhci_set_clock is now a library function
thats called from platform clock handler, make changes to address that]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The MSM SDHCI controller requires SDR104 mode to be set for HS200
cards. To handle this case, implement uhs_set_signaling so that
the mode selection for MSM SDHCI doesn't happen in sdhci driver.
Change-Id: I901dc82312b4299e86a7812dd74d3682650966a2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: Fix fn signature for set_uhs_signaling
that changed as part of 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Set the dma_mask to 0xffffffff to indicate full 32-bit
address space and thus avoiding unnecessary buffers bouncing
from high to low memory.
Change-Id: Idaffe14d4e54a27b15e5a5d82dad41d843714d57
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add support for hardware based card detection for external
SD card slot.
Change-Id: I3e081f2eff54d6932a89f826cc85c201c52ca840
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: Fix arguments for mmc_gpio_request_cd
as the signature had changed in 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Vote for the MSM bus bandwidth required by SDHC driver
based on the speed and bus width of the card. Otherwise,
the system clocks may run at minimum clock speed and
thus affecting the performance.
Change-Id: Icf0c8710adbe2770f4eae283a50f4a13671f703f
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Vote for PM QOS by specifying the acceptable CPU to DMA latency
so that system can enter into the possible power states without
affecting the SDHC performance.
Change-Id: I5fcf9aa93da690c6e64ab70ea5b039ca663c80ad
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict and compilation
errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Enable config MMC_CLKGATE to enable aggressive clock gating framework that
will disable clocks when the host is not in use for 200ms.
Change-Id: I6bef5dc18b561871689b3d730fd3486323b12520
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: sdhci_set_clock is now a library function thats
called from platform clock handler, make changes to address that]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This patch adds a function to configure adma descriptors to
support request size upto 512MB.
Change-Id: Ie2ad32106422bb5bdbf72b08d1ecdd74d9a93c19
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Enable MMC_CAP_HW_RESET capability so that MMC block layer
can reset the hardware during error recovery scenarios.
Change-Id: I6100a3c6c34ee4c965595e422f793b195a758a46
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Implement platform_execute_tuning and toggle_cdr callbacks that are
needed to support HS200 and SDR104 bus speed modes. Also, set
IO_PAD_PWR_SWITCH control bit in vendor specific register if
the IO voltage level is within low voltage range (1.7v - 1.9v).
Change-Id: If41704758d097229ffc0204d581886e137e8b581
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: Rename tuning ops fn to platform_execute_tuning]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
MSM SDHCI controller doesn't support tuning as specified by the
Standard Host Controller 3.0 spec. As a result of which,
CMD CRC errors are expected for tuning commands. Hence, add a
new quirk SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING to ignore
those errors for tuning commands.
Change-Id: Id43d300bf8fabea921c80931fbf45cd3782ff3fa
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Initial version of Qualcomm SDHC has the following two h/w
issues. This patch adds s/w workarounds for the same.
H/W issue: Read Transfer Active/ Write Transfer Active may be not
de-asserted after end of transaction.
S/W workaround: Set Software Reset for DAT line in Software Reset
Register (Bit 2).
Added a quirk SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT to enable this workaround.
H/W issue: Slow interrupt clearance at 400KHz may cause host controller
driver interrupt handler to be called twice.
S/W Workaround: Add 40us delay in interrupt handler when operating at
initialization frequency(400KHz).
Added a quirk SDHCI_QUIRK2_SLOW_INT_CLR to enable this workaround.
Change-Id: I8b4062f101085adadd66560f77b98b04d75cb836
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This patch adds the pad and tlmm configuration to msm-sdhci
driver.
Change-Id: Ic2b9beffdb555598bdc15b4b03c8adb78fbd0c2c
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This platform driver adds the support of Secure Digital Host
Controller Interface compliant controller in MSM chipsets.
Change-Id: Ide3a658ad51a3c3d4a05c47c0e8f013f647c9516
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflicts and Changed
Qualcomm to Qualcomm Technologies, Inc.]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The upstream sdhci-msm driver has diverged, removing the upstream version
to recreate our internal tree from msm-3.18 to msm-4.4.
Change-Id: I952b08667177272fdc30fea79b445f96a3fc2182
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Avoid retrying using single block for read commands that
fail with MMC_BLK_DATA_ERR. The single block read retry
is needed only in case of a CRC error for which
MMC_BLK_ECC_ERR will be set anyway by mmc_blk_err_check().
Change-Id: Iec9487fd73ecf2bdd5e62732cd42cdb3a639d0dc
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The data complete interrupt is also used to indicate that a
busy state has ended. Fix a race condition between sdhci_cmd_irq()
that sets any cmd err and sdhci_data_irq() (received to indicate
end of busy state) that clears cmd error. This can happen when a
cmd err is set and finish tasklet is scheduled but sdhci_data_irq()
executes before the tasklet. The cmd err status is critical for the
tasklet handler to reset the controller's state machine. This
should be cleared only when we have successfully processed a sbc
command and are ready to submit the actual command next, not when
there is an actual cmd err.
CRs-fixed: 733074
Change-Id: I91ea2b949c34446fb629446aabb21505734e27bb
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Disable HS200 mode until all msm-3.10 mmc changes have been
ported to msm-3.14. This avoids potential hangs at boot.
Change-Id: Ifc3dfbad59705db86c133b26baef0bc739a5dc30
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
SDMA buffer boundary size parameter in block size register should only be
programmed if host controller DMA is operating in SDMA mode otherwise its
better not to set this parameter to avoid any side effect when DMA is
operating in ADMA mode operation.
Change-Id: Ia29ca4759ead2e4c9ea1d72908444a03bf205bac
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Certain Samsung eMMC meet multi read timeout, and could not
reponse status CMD anymore after that. Add long read timeout
fixup to resolve it.
Change-Id: Ibeb0e6ab3d889d48fdee91244bec720a6994b907
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
[venkatg@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In order for this driver to function as a drop-in replacement for the
msm-3.10 driver:
- Allow selectability on ARCH_MSM
- Rename clock names to include _clk prefix
- Change supported compatible string
Change-Id: I20bc683512ebdd22fcd7845c7e43dd645a2f146f
Signed-off-by: Georgi Djakov <gdjako@codeaurora.org>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
[venkatg@codeaurora.org: fix kconfig options conflict]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The new request notification test checks the following scenario:
A new request arrives after a NULL request was sent to the mmc_queue,
which is waiting for completion of a former request.
Change-Id: I05db0959ded400e292eb5e84e1ecfc579b78ee62
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
[merez@codeaurora.org: fixed conflicts due to removal of BKOPS tests]
Signed-off-by: Maya Erez <merez@codeaurora.org>
[venkatg@codeaurora.org: Drop changes to mmc_block_test.c]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Enable the compilation of eMMC4.5 unit-tests, required by APT team.
This will allow the APT team to test the storage activity on released
builds.
The storage tests are disabled in normal operation and in order to
activate them a test I/O scheduler should be chosen and the test should
be triggered via debugfs. Therefore they have no effect on normal eMMC
driver operation.
Change-Id: I179c567f67cc8fab9ed1edab8246483de18bc76a
Signed-off-by: Maya Erez <merez@codeaurora.org>
[venkatg@codeaurora.org: Fixed trivial merge conflict]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
(cherry picked from commit 011e507b413393eab8279dac8b778ad9b6e9971b)
Running mmcqd as a prio 120 thread forces it to compete with standard
user processes for IO performance, especially when the system is under
severe CPU load. Move it to a SCHED_FIFO thread to reduce the impact of
load on IO performance.
Signed-off-by: Tim Murray <timmurray@google.com>
Bug: 25392275
Change-Id: I1edfe73baa25e181367c30c1f40fee886e92b60d
Add tracepoints to record the start and end of each mmc block
operation. This includes read, write, erase, secure erase,
trim, secure trim1 and secure trim 2, discard and
sanitize commands.
Change-Id: Ic5d1cbdb9adb940d8b1a2a13c73970023575df50
Signed-off-by: Ken Sumrall <ksumrall@android.com>
This reverts commit 829b6962f7.
Revert this change as it causes a sysfs path to change and therefore
introduces and ABI regression. More precisely Android's vold is not being
able to access /sys/module/mmcblk/parameters/perdev_minors any more, since
the path becomes changed to: "/sys/module/mmc_block/..."
Fixes: 829b6962f7 ("mmc: block: don't use parameter prefix if built as
module")
Reported-by: John Stultz <john.stultz@linaro.org>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
CONFIG_EXPERIMENTAL has been removed from the kernel, so clean
up its use in MMC_EMBEDDED_SDIO and MMC_PARANOID_SD_INIT options.
Change-Id: If414c265134b36740a84564274a631803c8e81b4
Cc: Arve Hjønnevåg <arve@android.com>
Cc: San Mehat <san@google.com>
Cc: Android Kernel Team <kernel-team@android.com>
Reported-by: Jon Medhurst (Tixy) <tixy@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Add some logging to make it clear just how the emmc timeout
was handled.
Change-Id: Id33fd28d8b9778dc4e85db829e2637a328eddab4
Signed-off-by: Ken Sumrall <ksumrall@android.com>
mmc_sdio_init_card function is doing necessary initialization
Change-Id: I7d2e432b2af8a76267378acba07e3e4e8fd1e6bc
Signed-off-by: Hosung Kim <hosung0.kim@samsung.com>
