This is needed for supporting 64-bit kernel.
Change-Id: Id4f60dc15688a6f02f31d77705ad1ef0181a1ce9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In the current code, if sdhci_check_state returns true a tasklet is
scheduled which doesn't complete the request if host->mrq is NULL,
which is the case, if sdhci is in bad state. This would make the
mmcqd thread wait for completion infinitely.
Hence, complete the request if sdhci_check_state returns true instead
of scheduling the tasklet.
CRs-Fixed: 615537
Change-Id: I8e2950c3999ac3806f9d631c52d86f0dc13b992f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
In some cases, it is possible that the hardware might trigger
an interrupt just about the same time the software tries to
reset the controller. In such case, the hardware interrupt will
be handled after the current thread release spin lock. This leads
to spurious interrupt handling after the completion of reset.
Change-Id: I75211adee1179b0636a918f5ceb68a072ad02a6c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
If cpu-dma-latency is not defined in dts files, set it
to 200usec
Change-Id: I27b0357b4d88842a258332250bae66efac3ee5e2
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
There is a new header file for 64bit platforms.
Change-Id: Iead9ccab1fd0b7249baf670e67872fcffeccf21d
Signed-off-by: Raviv Shvili <rshvili@codeaurora.org>
Add support for Linux pin control framework while also supporting
the older TLMM configuration for backward compatibility
CRs-Fixed: 568232
Change-Id: Ib6b8f41fd6ced9aa62c980d7e4a73469603cbc5b
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
With commit 0797e5f145 (mmc: core: Fixup signal voltage switch), voltage
switch sequence for UHS-I cards is broken if used with sdhci driver.
The commit expects the SD clock to be disabled when mmc_set_ios() is
issued but sdhci_do_set_ios() re-enables the SD clock for few cycles
after disabling which is a specification violation during voltage
switch sequence. This failure is observed only for a small group of
cards where they ultimately fall-back into high-speed mode even if
UHS-I modes are supported.
Change-Id: Ie275326627a84bfcd4352637a043296c01c175a6
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
CLK_PWRSAVE bit in vendor specific register gates the output clock to
card automatically if there are no data/cmd operations.
According the SD3.0 voltage switch sequence the host should provide
clock to the card for atleast one millisecond before DAT[3:0] lines
are pulled high by the card. In this case if power save bit is enabled
it might auto-gate clocks even before the card completes voltage
switch sequence.
Fix this by disabling power save operation when the clocks are turned
off and enable only when clock rate is >400KHz i.e., end of initialization.
CRs-Fixed: 589992
Change-Id: If82d6d2e303b8d1189b76712e514f41fe6e2cf8b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Remove maximum timeout for all cards, since this causes
a long resume time for SD cards. Now only Hynix cards would
have this maximum timeout and this would be decided at the core
layer.
Change-Id: I758f9e5ecf407aba371928a86c313cf69e3cda63
CRs-fixed: 587284
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
With SDCC5 the capabilities register is not advertising the
8-bit capability feature (except for 8974 and 8084).
So add the software capabilities for 8-bit slot for rest of
the targets with SDCC5.
Change-Id: I288292f37d77507bf5aaa44bf156496b4df87234
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
With SDCC5 the capabilities register is not advertising the
3.0 voltage features (except for 8974 and 8084).
So add the software capabilities for voltage initialization
for rest of the targets with SDCC5.
CRs-Fixed: 568227
Change-Id: Ida53f5ad7249cd0cd8428b4839dfd932b04e31fa
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
A callback to turn-on the controller clocks is implemented.
This callback would ensure that the pclk and mclk are enabled
but the output clock to the card is disabled.
CRs-Fixed: 567658
Change-Id: Ic97e600a6388fb64f1267a097b201f31d114a1fb
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Currently, the clock to the card is enabled prior to enabling
the power to card. Specification requires that the power be
supplied first and then a delay of 10ms and then clock be
provided to the card.
In this, during MMC_POWER_UP mode, the controller clocks would be
ON and the power would be supplied to the card. In the MMC_POWER_ON
mode, the clocks to the card would be enabled and the rate set.
A callback has been provided to facilitate the enabling of
controller clocks.
CRs-Fixed: 567658
Change-Id: I2d66eae1581b9b136faaba4cafc330aeb6a3f364
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: Fix sdhci_set_power fn signature
as it changed in 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Several data-timeout issues were seen, most of which were
due to the card taking a longer time to respond. This patch
increases the timeout of the controller to 0xF i.e. max
possible.
Change-Id: I6739de3eb5d9cccf8e39d9dc4730056782334162
CRs-Fixed: 536832
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
On machines that support more than 32-bit address via lpae or 64-bit buses
set the dma mask as 64-bit.
Change-Id: Ida88f3999fd5e7d09ebe73bb3481d3f1f4cf30c2
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
MSM SDHCI has CDR mechanism (clock-data recovery) to
automatically adjust the sampling point based on the
voltage/temperature variations. This must be enabled
for only read. Hence, add new host op toggle_cdr to
control CDR.
Change-Id: I75940cfca15fe88de6d46fe58cb33620a3b7ced1
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Currently, the sdhci host lock is initialized in sdhci_add_host()
but there can be a case where it is required even before that.
Hence, initialize it in sdhci_alloc_host() where sdhci_host
structure is allocated.
Change-Id: If99d82679c07bc2d36e0aad9354757288aa400b8
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Some platform drivers support more than 128 adma descriptors
and allows more than 512KB maximum request size per transfer.
Add a callback to get maximum supported adma descriptors from
platform driver instead of limiting host capabilities to
128 descriptors.
Change-Id: I0ac0ffbd0e792a76931e21b321b39c35195ac8d6
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
During probe disable the HC mode since the reset is done in
SDCC mode. HC mode will get set after the reset is complete
before the rest of the initialization is done.
Change-Id: I1fdc633c218447c15c8caad24e2805e7510088f2
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The SD3.0 voltage switch sequence to 1.8v would involve stopping the
SDCLK before changing the voltage level and with recent changes in 3.10
kernel, the peripheral clocks are also getting disabled instead of
just stopping the clock to the card. This patch makes sure this doesn't
happen by marking the flag card_clock_off in struct mmc_host before
starting the voltage switch sequence and checking it in host controller
driver.
Change-Id: If62378ba1dd369e69524365a4421d57317c22ca2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The power save bit is currently enabled based on the clock
rate (clk_rate > 400KHz) within struct sdhci_msm_host. But this
clk_rate is updated with the latest value down in this function
sdhci_msm_set_clock(). So during runtime/system resume when the
card is still in initialization phase, the power save bit is
getting enabled when sdhci_msm_set_clock() is called for the
first time based on the previous rate which is wrong.
Change-Id: I05dc8a4a760f658935de3831aaf8dd3b2b996466
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Enable power save feature within controller by setting bit 1
in vendor specific register (0x10C). This allows controller to
disable SD clock when bus is idle to save power.
Change-Id: I916a5a414adb3f21dc3a75f3f86c3a81d6956dc8
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch enables automatic calibration for eMMC devices
in using auto-command21. This feature is disabled by default
and can be enabled using the sysfs attribute
'enable_auto_cmd21'.
CRs-Fixed: 516314
Change-Id: I020c61cb9dee56c0ebe37864e67e4753ddee1adc
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This patch adds Programmable Delay Line auto-calibration
support if supported by respective hosts.If the host
supports auto-calibration this change would enable
sending CMD19/CMD21 before any read operation.
CRs-Fixed: 516314
Change-Id: I8a0f51206dc0e174519dd71f0c75267a9e08e7f7
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
As per specification, auto cmd error status register is valid only
when auto cmd error bit is set in Error interrupt status register.
CRs-fixed: 515513
Change-Id: Id1013e1705d8efdba0171dcad14f783607d38ef3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
In HS400 mode a new RCLK is introduced on the interface for read data
transfers. The eMMC5.0 device transmits the read data to the host with
respect to rising and falling edges of RCLK. In order to ensure correct
operation of read data transfers in HS400 mode, the incoming RX data
needs to be sampled by delayed version of RCLK.
The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be
initialized, configured and enabled once during HS400 mode switch and
when operational voltage/clock is changed.
Change-Id: Ie7acc50cb932a7b531434ebe72f78e2e7ad27408
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The following msm platform specific changes are added to support HS400.
- Enable CDC calibration fixed feedback and sleep clock.
- Allow tuning for HS400 mode.
- Add capability to parse and configure pull settings for RCLK pin.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.
Change-Id: I1304fe0f01df493ead48bf9ff3c7baee5ab040d4
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The request to change the VDD I/O voltage level to high/low will
trigger an IRQ only when -
1. SWITCHABLE_SIGNALING_VOLTAGE bit 29 of SDCC_MCI_GENERICS register
is set.
2. Above condition is true and when there is a state change in VDD
bit 3 of SDHCi Host Control 2 register.
Until now, the MMC core layer issues I/O high request only after
the controller is powered up. The I/O high request is same as the reset
state of host control2 register which will never trigger an IRQ. The
driver already handles this case by ensuring that I/O voltage is set
to high as part of power up itself and thus returns immediately when
I/O high request is issued later. But in 3.10 kernel, this request is
issued even before the controller is powered up. Hence, check for
host->pwr state to avoid waiting for an IRQ that never comes.
Change-Id: I31b6723f53397be1ba151305ead89e739560eb20
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Some SDHC controllers are unable to handle data end-bit
errors in one bit mode.
This patch adds a quirk to ignore data-end-bit error in
1-bit mode in Qualcomm SDHC controllers.
Change-Id: Ica0f10573d654021449c32197b126e12bb1a3c10
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: sdhci_clear_set_irqs was removed
from 3.14 kernel, write the registers directly]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict and fixed
the bitmap for the quirk macro]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Implement dump_vendor_registers host operation to print the
vendor specific registers in addition to standard SDHC
register during error conditions.
Change-Id: I347e8f0373264574a80e460967afba6859607ac9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add new host operation dump_vendor_regs to provide a
mechanism through which host drivers can dump vendor
specific registers in addition to SDHC registers
during error conditions.
Change-Id: Ifba3ddcb18c3c0917343d99fe58d5ed04b2da871
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The auto command error interrupt is not enabled now. Hence,
if there occurs a timeout when auto-cmd is in progress,
no data timeout interrupt would occur and the driver would
only timeout after the software timer expires.
This patch enables the auto command error interrupt and lets the
higher layers know of such an error, if any.
CRs-Fixed: 515513
Change-Id: I69880a72ece7730645dcfe699d58271d60cab33d
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This patch adds support to configure regulators only if
it is defined in dts files. However, it doesn't return an
error otherwise.
Change-Id: Iac2284b2df3b3d8af623da0f17697694994b34b8
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This flag ensures that the power to the sdio card is not
cut-off. That way this can wake-up the device when required
using asynchronous interrupt mechanism.
Change-Id: Ic91bfdc93e117c5e627360a4d0ef80f661aa1b60
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Provide sysfs tunables to defer PM QoS vote of default value so that
back-to-back requests wouldn't suffer from latencies caused by CPU
power collapse transition states.
Change-Id: I7180c68c1f13240faa5f432335d72e7f6b198183
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
PM QoS vote of default value mean that the CPU is allowed to move
into deepest low power mode whenever possible. Currently, if there
are back-to-back MMC requests, with a short delay, the PM QoS vote
to default value is done immediately which cause the immediate
request to have high latency as the CPU might have idle'd and moved
to deepest low power mode. To avoid this defer the PM QoS vote till
a defined timeout (pm_qos_timeout_us), so that back-to-back requests
may not suffer from additional latencies.
In addition, if the load on MMC is low, the additional latency may be
sustainable. Hence, aggressively release the vote in order to achieve
additional power savings.
CRs-Fixed: 501712
Change-Id: I82166b0ce9416eb0d519f7da26e5a96956093cb2
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict and fixed
compilation errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The specification indicates that the tuning process is normally
shorter than 40 exections of tuning command. Hence, retry the
tuning sequence for at least 3 times before returning the error.
Change-Id: I21724a73af7b997e128b56a2600bdcb12e414996
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add support for polling by providing sysfs entry. It can be
enabled/disabled, by writing 1/0 respectively to the sysfs node -
sys/bus/platform/devices/msm_sdcc.<slotno>/polling. The polling
will be available only if hardware based card detection is not
supported.
Change-Id: Ic58c36665e23cb921d76c482494a168289e83b83
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
MMC_CAP_HW_RESET capability was only referring to host driver
capability to toggle eMMC RST_n pin so if the host driver is
unable to toggle this pin, it shouldn't advertise this capability.
CRs-Fixed: 507926
Change-Id: Ia1408d95503d19ae0f7c49c7bb7905b0ddaddbd5
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The driver currently uses fixed timeout value from capabilities
register (bit 5-0) to calculate the timeout which is advertized
as 50MHz. But the driver uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK
and controls the base clock (MCLK) directly. So during card
initialization, the frequency would be 400KHz but still timeout
is calculated at 50MHz which is wrong. This patch fixes this by
using the current base clock frequency to calculate the timeout.
The controller internally multiplies the timeout control register
value by 4 with the assumption that driver always uses fixed
timeout clock value from capabilities register. Add a quirk
SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 to avoid this multiplicaiton in
case base clock is used for timeout calculation.
CRs-fixed: 498159
Change-Id: I503fd16132bf17e590239997d6970b9b730d4202
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off.
As SDCC driver is capable of handling the asynchronous interrupt,
advertise MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE capability.
Change-Id: Id5a86bc70b7b798b23be3a0fc0d59b2db05e0409
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDCC controller provides the PWRSAVE control bit to automatically
disable the clock to card when there is no activity with card.
During the SDCC DLL tuning, PWRSAVE is disabled to make sure that clock
is always running but once the DLL tuning is completed, currently we
enable the PWRSAVE unconditionally irrespective of its previous state.
This change ensures that we always check if the previous state of pwrsave
before really enabling it.
Change-Id: I464ab1e0db41af50550bb5a9ea9b909ee0d27dd9
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The drivers must do clk_set_rate() before the first
clk_prepare_enable() is invoked. Otherwise, the clock
driver may give a warning for such clocks.
CRs-fixed: 493685
Change-Id: I8342aa2f35d64a4dc7b8396bd9741c0aecaedc5c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Enable MMC_CAP2_CD_ACTIVE_HIGH capability if the card-detect
gpio polarity is active high.
Change-Id: I80e869dd7ecb6e24e81d1cc73ef8101c44110873
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
The current driver just enables "iface_clk" before accessing its
registers but MSM bus clocks are also required for register access
without which any register access would result in chip reset.
The MSM bus clocks can be enabled by setting vote to MSM bus bandwidth
driver. Currently, voting is being done in sdhci_enable/disable but these
functions will not be invoked by MMC core layer for some cases such
as mmc_power_up/mmc_power_off, which require peripheral register
access.
To resolve the above mentioned problem, bus voting and de-voting will
now be done as part of clock management within the sdhci MSM driver
i.e., before enabling SDHC clocks and after disabling SDHC clocks.
Change-Id: Iff608fba4c58bf37a6f4ce8eb36876c79969feaf
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The SDHC driver registers sdhci_led_control() with LED class device
and it gets invoked when the sysfs entry - /sys/class/leds/mmcX::
is updated. This function access SDHC Host control register (0x28)
and hence, check the driver state (runtime suspended/clocks gated)
before accessing it. Otherwise, it may result in unclocked access
resulting in system failure.
CRs-fixed: 480596
Change-Id: Icef51f02abb54316710df30429fec875030d42d9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
SDCC controller reset (SW_RST) during probe may trigger power irq if
previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
enable the power irq interrupt in GIC (by registering the interrupt
handler), we need to ensure that any pending power irq interrupt status
is acknowledged otherwise power irq interrupt handler would be fired
prematurely.
CRs-Fixed: 487962
Change-Id: If4693869210bc8b361dadb2b68a47b6ac8707e0f
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Wait for SW reset to be complete before proceeding further
in probe. Otherwise, any register writes immediately
after the reset would be ignored/reset.
Change-Id: If1c7f5debfca6f45a0fdb08bc759ad04b96fd86c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
The version register is only 16 bits wide but we use a readl to
read it. Normally this wouldn't be a problem, but the register
offset is 0xfe, something that is not word aligned. This causes
crashes on THUMB2 kernels. Use readw instead to read the register
properly and avoid any alignment issues.
Change-Id: I3b8b14ce2f741631ef7554e3763d1d7f145077a8
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
