Add the following devices that are present in pmicobalt.
- 6 LPG channels from address 0xb100-0xb600 along with LPG_LUT
@ address 0xb000.
- LABIBB regulator device that can support configuring LAB and
IBB modules @ address 0xde00 and 0xdc00.
CRs-Fixed: 1005724
Change-Id: Ic252e83f8a7273796ddc0e42c0ae37f339931499
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Remove unused legacy bus code and APIs
CRs-Fixed: 1006336
Change-Id: I15811b787b54004e1aaba859e4c911be8f9eb285
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Remove write-back and rotator related obsolete code in order to reduce
dead code maintenance.
CRs-Fixed: 987777
Change-Id: I917d9b5b777fb41f3f87213d8d9e6e7ddf73f92c
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Issue: CSIPHY IRQ enabled when kernel recivies possible sof freeze
and will not disable if there is no csiphy release call from backend
which inturn leads watchdog bark.
Resolution: Dump the CISPHY IRQ at the time of possible sof freeze
and disable them.
CRs-Fixed: 996571
Change-Id: I3c6040b81c04660d3a0ac7ed707e1f4b22498dbd
Signed-off-by: Ramesh V <ramev@codeaurora.org>
Use QCOM_BUS_SCALING as opposed to MSM_BUS_SCALING
Change-Id: I23945a040914d55aa483cfec6ef81e7342421f2e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Enable CONFIG_SCHED_HMP_CSTATE_AWARE in order to optimize task
placement with CPUs C-state. This brings better system performance.
CRs-fixed: 1006303
Change-Id: I18e62015371143bca56396c747eaad3b22c5e3a3
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Update CPU efficiency property for msmcobalt so that scheduler can utilize
for task placement decision.
CRs-fixed: 1006303
Change-Id: Ifb59d6b1fcb1207053438786df2472417a2db93f
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
At present among the same power cost and c-state CPUs scheduler places
newly waking up task on the most loaded CPU which can incur too much of
task packing on the same CPU. Place onto the most loaded CPU only when
the best CPU is in idle cstate, otherwise spread out by placing onto the
least loaded CPU.
CRs-fixed: 1006303
Change-Id: I8ae7332971b3293d912b1582f75e33fd81407d86
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
There are CPUs that don't have an obvious low power mode exit latency
penalty. Add a new Kconfig CONFIG_SCHED_HMP_CSTATE_AWARE which controls
whether CPU C-state is used to guide task placement.
CRs-fixed: 1006303
Change-Id: Ie8dbab8e173c3a1842d922f4d1fbd8cc4221789c
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Update the wakeup placement logic when need_idle is not set. Break
ties in power with C-state. If C-state is the same break ties with
prev_cpu. Finally go for the most loaded CPU.
CRs-fixed: 1006303
Change-Id: Iafa98a909ed464af33f4fe3345bbfc8e77dee963
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
[joonwoop@codeaurora.org: fixed bug where assigns best_cpu_cstate with
uninitialized cpu_cstate.]
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Try and find the min cstate CPU within the little cluster when a
task fits there. If there is no idle CPU return the least busy
CPU. Also Add a prev CPU bias when C-states or load is the same.
CRs-fixed: 1006303
Change-Id: I577cc70a59f2b0c5309c87b54e106211f96e04a0
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
Update ucode workarounds for A5xx GPUs based on new
microcode and hardware changes.
CRs-Fixed: 1000396
Change-Id: I87a1ba9bfc441cad2ed6a6959d07af1cc1e2c7bc
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
Driver is overriding the ep0 request context with gsi driver
context even if it does not intend to handle the setup completion.
This is causing flood of warnings when composite_setup_complete()
is type casting the function driver context as cdev and failing to
match ep0 request pointer with cdev->req. Hence only override
context when driver is overriding the complete call back.
CRs-Fixed: 1003784
Change-Id: I176671ae09f17d920643eeeec8262a6f97856712
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Use "gadget->dev.parent" instead of "&gadget->dev" in the first argument
of dma_zalloc_coherent() because the parent has a udc controller's device
pointer. Otherwise, iommu functions are not called in ARM environment and
allocation is failing.
CRs-Fixed: 1003784
Change-Id: I2ea75b533f857189856840e437a96891eea5699c
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
In case gsi_update_function_bind_params() returns failure
before initializing spin lock for event queue, gsi_bind()
continues further by calling post_event() which acquires
the uninitialized spin lock causing BUG. Hence check for
return value of gsi_update_function_bind_params() before
calling post_event().
CRs-Fixed: 1003784
Change-Id: I0fcad2467d15f311feecf3b9cee9209f7453485c
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Adds support to allocate specific hardware EPs to
GSI enabled endpoints. Creates EP list with names
"gsi-epin" for IN and "gsi-epout" for OUT EPs that
are intended for use by the GSI function driver.
The EPs are reserved from the end of the EP list.
CRs-Fixed: 1003784
Change-Id: I70ebce8c2717baaea38f7b6235976d8a522eb9fd
Signed-off-by: Devdutt Patnaik <dpatnaik@codeaurora.org>
This allows configuration of event buffers for GSI based
hardware accelerated endpoints.
Change-Id: If9ae84c0de214bcb5057d14a6960b6fb528c6c14
CRs-Fixed: 1003784
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Add additional event buffers for GSI based hardware accelerated
endpoints and its related configuration.
CRs-Fixed: 1003784
Change-Id: Ibedf73690040b8bd872f5621835680a66c22e265
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Enable smart prefetch control for xDCI channels.
This is done by configuring the channel scratch in GSI.
Change-Id: I9a301da3c5426649b40069103d545e50bc75aad2
CRs-Fixed: 1004467
Signed-off-by: Gidon Studinski <gidons@codeaurora.org>
Enable smart prefetch control for MHI channels.
This is done by configuring the channel scratch in GSI.
Change-Id: Icff18699ce96e224d6f58b8aadce006f3d5210ee
CRs-Fixed: 1004468
Signed-off-by: Gidon Studinski <gidons@codeaurora.org>
APR packet size is now capped at 512 bytes. The codec register
config data is 740 bytes. We now break up this data into multiple
packets no larger than the defined maximum.
CRs-fixed: 974874
Change-Id: I2bd3cb01ff389ffd1d319239019e11d35d8c16b6
Signed-off-by: Stephen Oglesby <soglesby@codeaurora.org>
RTC driver is responsible for reading RTC value
and also used for reading/setting Alarm value.
This patch enables QPNP RTC config.
Change-Id: Ibc2aee233e657ba73b42f41e9b20859e818d9e1d
Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
Make sure that DMA ops are initialized before attempting to allocate
the DMA substream buffer.
Change-Id: I03bcb4ac7ea415c00ce3047b844455f5c6546400
Signed-off-by: Shiv Maliyappanahalli <smaliyap@codeaurora.org>
It is possible that the extcon notifier may be triggered
soon after it is registered, but before the mdwc->dwc3
has been populated. This leads to a NULL pointer dereference
in vbus_notifier. Fix this by moving the extcon_register()
call later in the probe until when the the driver would be
ready to handle an immediate notification.
CRs-Fixed: 1003908
Change-Id: I403da246f18c25a77fa7f66e152cbcdca8c00b16
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Add #ifdef CONFIG_CNSS_SECURE_FW for cnss_get_fw_ptr and
cnss_get_sha_hash.
Change-Id: I884b4ab3d552b12dd83f852be565a5dc4e69e21a
CRs-Fixed: 971688
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
In order to enable prefetch control in GSI,
channels needs to be configured to doorbell mode.
CRs-Fixed: 1000819
Change-Id: I4847982f48b09de1690bb474db9a60e018e0c0d6
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
User space function driver could always provide descriptors for all
speeds irrespective of USB speed supported with USB gadget. If USB
gadget is not high/super speed capable, f_fs driver doesn't parse
HS or SS descriptors which results into OS descriptors processing
fail due to checking against wrong offset within received descriptor
buffer. Fix this issue by always processing HS and SS descriptors
without checking USB gadget speed.
CRs-Fixed: 1003565
Change-Id: Icb6537271ce55e44f5fc3e1ef28dd4d6810b681f
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Add the initialization and shutdown programming sequence for the DSI PHY
v3 which is used on msmcobalt. This includes configuring the phy lane
timings, strength control, and regulator settings.
CRs-Fixed: 1000724
Change-Id: I6a8d45ef71316b5a935a711a5b0a48c055c1c392
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add PHY timing calculation support for v3 PHY used on msmcobalt.
This needed to program the DSI PHY to drive the link at a specific
link rate based on the DSI panel configuration.
CRs-Fixed: 1000724
Change-Id: I180af3544c111cb9f491ea9fb77638beece8299c
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Refactor the DSI PHY timing calculations for v2 PHY. This will make things
easier when support has to be added for new revisions.
CRs-Fixed: 1000724
Change-Id: Icd99a3b29feddc64e42a2b4a18987579b7f52e77
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
DSI controller version 2.0 and above require configuring an additional
link clock called the byte interface clock which is used to drive all
high-speed PPI signals. Add support to configure this clock.
CRs-Fixed: 1000724
Change-Id: I907823b21ad2c6152899233fc52f38d17bcc5ed1
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
For certain board configurations, the enable port on display
connector card needs to be controlled via LCD mode selection
GPIO. For example, for DSC/single DSI mode, the GPIO needs to
be driven high and for non-DSC/split DSI mode, the GPIO
needs to be driven low. Add support for this.
CRs-Fixed: 1000724
Change-Id: I3546fc2b5dacd77e9d2cd2ea843481dc34bfef54
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
For split-DSI hardware configuration, both the DSI controller clocks are
sourced from a single PLL (clock-master). In such cases, it is important
to initialize both DSI0 PHY and DSI1 PHY prior to enabling the PLL.
This is due to the fact that for certain HW versions, PLL programming
for the clock-master may require configure some PLL registers on the
clock-slave. If the PHY init sequence for the clock-slave is called
after PLL is programmed, it could reset those PLL registers leading to
unexpected behavior. Fix this by ensuring that PHY init sequence is done
for both controllers at the same time for split display usecases.
CRs-Fixed: 1000724
Change-Id: I09fb8097d31cd0390cea5c32bb7aabceeff2c37e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Since driver context f_cdev is not freed until the driver
is unloaded, port_usb remains available to be accessed for
driver operations. Hence there is no need to protect port_usb
using spin lock. Hence remove un-needed spin lock/unlock from
some of the APIs which prevents recursive spin lock. Also, make
sure char device is destroyed before f_cdev context is freed up.
Change-Id: Ib91f23c070065185da72387300304f2690d5a8b1
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
When l1_supported is false and USB gadget max speed is high speed
only, composite framework is not updating bcdUSB as 0x0200 which
results into bcdUSB set as 0x00 used as part of device descriptors.
This is against USB specification and also USB host may behave
differently. Fix this issue by setting default value of bcdUSB as
0x0200.
CRs-Fixed: 1006330
Change-Id: I8330f0609540d97f5bca78c42ed193537f497a73
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
wsa881x codec shutdown gpio is connected to msmcobalt and
control of this gpio happens through pinctrl. Add support
in codec driver to enable/disable gpio using pinctrl.
Change-Id: I9d627bf40f0e6be5d085eafc5e7211366e795c24
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
WCD and WSA codecs uses MSM gpios that are accessed through pinctrl
mechanism. Codec reset gpios need to be configured before master
controller is initialized otherwise codec cannot be enumerated
on the bus. Add a new platform device driver to update reset gpio
configuration to valid state before bus initialization.
Change-Id: I1e36f4a85334704652c6b50950f50b90224a472e
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
SP-PBL could be writing other values to err_status_spare2 register and
hence check for exact value to conclude its wdog_bite.
CRs-Fixed: 1005034
Change-Id: Iaef99256f86c2e6508554f2d144d1514f10e6049
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
APR is required not to send any packet until the far end queues
at least one intent. Add the wait during client registration time.
Change-Id: Ie29ddda4527ae7a70afff2c595d6e3c76500a8af
Signed-off-by: Deven Patel <cdevenp@codeaurora.org>
Signed-off-by: Josh Kirsch <jkirsch@codeaurora.org>
On few devices QPDI's LDOs are configured by some other component.
This change adds support to skip LDO configuration on such devices.
Change-Id: I84c8b4a5a0d6155a39e43e0503961f76e2d8a615
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add support to set default sink at probe time.
Change-Id: I62abe39a5cb5e7f8b1bb1198cecd3b529b124de8
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add support to switch to a different Coresight sink when one or
more Coresight tracing sources are enabled.
Change-Id: I79f769f0913124710ae56fddea7d205359e09b43
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Add remote etm driver in upstream implementation of Coresight
driver.
This change copies coresight-remote-etm.c file from drivers/coresight
(commit c1fe9ac38d93 ("input: touchscreen: correct function and variable
names in ITE tech driver"))
to driver/hwtracing/coresight directory.
Change-Id: I77a1aaf10aaf3f3010ab19d5878bb53dcc504c29
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Upstream's Coresight driver doesn't have id field in
coresight_platform_data. So use device name instead to link bus clk with
Coresight device node.
Change-Id: I9f70974d64154217c2701879eb428beef1857fcf
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
