Some of the common irq data is moved into a irq_common_data structure
within irq_desc structure.
Change irq_data references to irq_common_data structure to fix
compilation issues.
Change-Id: I59c99348a44d364d74af6b67ccabdd2d8c5008b0
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
MPM driver is required to configure the hardware to wakeup from SoC
sleep. It is currently not enabled for cortex targets.
Enable MPM_OF config for cortex targets.
Change-Id: I09313d7809ec939a9d0440d0ab30a5992f512b96
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
MSM_PM enables sleep modes for CPU subsystem. It is not currently
enabled for msmcortex target.
Enable MSM_PM for cortex target.
Change-Id: I67244ff55690c164634e9233e2d0cec3388c5be8
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Rename vdda18-supply as core-supply with USB QMP PHY on msm8996
and msmcobalt. Also provides required voltage value with this
core ldo for msm8996.
CRs-Fixed: 1001463
Change-Id: Ia826e361d8259126a8168c07539ba4b4f6053f65
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
On newer platform USB QMP PHY needs different voltage supply as core
voltage. This change adds required support for the same.
CRs-Fixed: 1001463
Change-Id: If100d36bade241dedf28e3cea9e07be192bdfdc2
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
USB QMP PHY requires CML based refclock, otherwise USB QMP PHY
PLL may not lock. Hence select CML based refclock by programming
SYSCLK_EN_SEL register.
CRs-Fixed: 1001463
Change-Id: I4cc68a447d0cf3571a50b18d7eec5415430f9423
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Update USB3_PHY_SW_RESET register's offset on msmcobalt otherwise
USB QMP PHY is not released out of reset.
CRs-Fixed: 1001463
Change-Id: Idc71b0abb24cf8c103dfde893ba8c40d342a7fb8
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
As long as GPMU is enabled, DCVS has to handshake with firmware.
It is a new requirement of A540 power management.
CRs-Fixed: 973565
Change-Id: Ie6480fc3ba0e1b95aab40e31b09ff2bd798ff30f
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
A3XX doesn't have support for command batch profiling. Return
EOPNOTSUPP for a command batch profiling request on A3XX, so that
userspace code knows that this feature is not supported.
CRs-Fixed: 986169
Change-Id: I6dfcab462a933ef31e3bba6bef07f17016ae50b9
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Current code incorrectly specifies buffer size as 0 for mapping
gpuobj user memory. This causes the map to fail because buffer
size is expected to be a non zero value. Fix this by passing the
correct size of the buffer to be mapped.
CRs-Fixed: 995378
Change-Id: I1a9aeb3f1dd67f014847322e5b14cba8775a82a4
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
In adreno_remove() there is possibility of dereference of gpudev
without NULL check. Fix this by getting gpudev after adreno_dev
NULL check.
CRs-Fixed: 993267
Change-Id: I17d8b4ba2c74a787a065dbdb0ac88d065605fcb1
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
For user memory of type KGSL_USER_MEM_TYPE_ADDR mapped to GPU driver
verify permissions and map GPU permissions same as CPU permissions.
If elevated permissions are requested return an error to prevent
privilege escalation. Without this check user could map readonly
memory into GPU driver as readwrite and gain elevated privilege.
Write permissions check is currently inverted causing readonly
user pages to be mapped as readwrite in GPU driver. Fix this
check to map readonly pages as readonly.
CRs-Fixed: 988993
Change-Id: I0e097d7e4e4c414c0849e33bcc61a26fb94291ad
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
The kernel command buffer is not zeroed in the adreno ioctls,
and may contain garbage. The garbage value can lead to
unexpected results.
CRs-Fixed: 993518
Change-Id: I75033cdf4637881ecd6fa4dd31aea083b134e6d2
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Current order:
IB1 batch, timestamp writes, SRM=NULL, CP_YIELD_ENABLE,
CP_CONTEXT_SWITCH_YIELD
Correct order:
IB1 batch, SRM=NULL, CP_YIELD_ENABLE, timestamp writes,
CP_CONTEXT_SWITCH_YIELD
Reason:
if preemption is initiated after the last checkpoint but
before SET_RENDER_MODE == NULL is executed, all of the PM4s
starting at the preamble of the check point will be replayed
up to the SRM == NULL, including an attempt to re-timestamp/
re-retire the last batch of IBs.
If what was intended here was to make sure that the IB batch
would be retired once then the SET_RENDER_MODE == NULL and
CP_YIELD_ENABLE should be placed immediately after IB_PFE packets
and before the time stamping PM4 packets in the ring buffer.
CRs-Fixed: 990078
Change-Id: I04a1a44f12dd3a09c50b4fe39e14a2bd636b24de
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Currently, Rx an Tx is based on workqueue and it is taking significant
time to schedule a workqueue which is hampering performance.
Use tasklet if underlying transport supports atomic context, otherwise
kworker is used.
CRs-Fixed: 978296
Change-Id: I736d2b90730ec10f9dff21944c4ad50e4d87da5c
Signed-off-by: Dhoat Harpal <hdhoat@codeaurora.org>
Lower the APM threshold voltage from 852 mV to 832 mV in agreement
with hardware guidelines. In addition, specify an APM hysteresis
voltage of 32 mV to help reduce the number of corners whose floor
voltages need to be raised to ensure stable operation with
manual APM switching.
Change-Id: Ida87a70395e8bfd1506166cfa02f5b48b1132269
CRs-Fixed: 1001346
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Adjust floor voltages based upon a configurable APM hysteresis voltage.
This reduces the number of corners whose floor voltages must be raised
to ensure stable operation with manual APM switching. In particular,
for corners with ceiling voltage greater than or equal to the APM
threshold voltage and floor voltage less than APM threshold voltage
set an adjusted floor of max(floor, APM threshold - APM hysteresis).
Change-Id: I65bebcfd8f4785bce9f65243987c05444aab14ee
CRs-Fixed: 1001346
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Increase the maximum floor to ceiling range of LowSVS and SVS
corners to 55 mV and Nominal and Turbo corners to 65 mV for
both VDD_APC0 and VDD_APC1 CPR devices. Also, increase the SVS
floor voltage to 572 mV in agreement with hardware guidelines.
Change-Id: Ida2a9ba842038ec2567344f1544e5b4f73794215
CRs-Fixed: 1001353
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Initialize the controller type before cpr3_parse_common_ctrl_data()
is called as this function performs initializations based upon
controller type.
Change-Id: I0cdcd6519338043e40acf9357f39a61ff6f43604
CRs-Fixed: 1001355
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Enable open-loop and target quotient interpolation for VDD_APC
CPR devices. Also, treat the scaled open-loop voltage as the
absolute ceiling for each corner. This ensures the CPR voltages
more closely track the silicon Vmin and prevents unnecessary
power consumption.
Change-Id: I8b1baad474a76553ac4094c09fc01b1ea0a4646a
CRs-Fixed: 1001350
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Currently, open-loop voltage interpolation is skipped for corners
mapping to the highest fused corner thus resulting in incorrect
open-loop voltages when open-loop interpolation is enabled. Fix this.
Change-Id: Iab5a2dadfec45efb08b9c45f956e9f102d2d2c55
CRs-Fixed: 1001350
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Read commands are currently assigning 64bit physical address
to 32bit token. There is a possibility that this physical address
may have same lower 32bit values which could cause errors. Fix
by assigning session id as the token value.
Change-Id: Ie704e34338201ecec191b2031d20552691aed3ea
Signed-off-by: Shiv Maliyappanahalli <smaliyap@codeaurora.org>
Use tokens to track all active no wait commands.
In ASM driver, certain commands are waited on to get response
from ADSP. There is a possibility that certain no-wait
commands can be improperly recognized and woken up leading
to time outs.
Change-Id: I2030a354493845b63cf92d35ca4eaadef38cfb79
Signed-off-by: Shiv Maliyappanahalli <smaliyap@codeaurora.org>
The default configuration for AD config_buffer_mode register is correct
for dual DSI case, but not for single DSI case. This change correctly
set the AD config_buffer_mode for single DSI case.
Change-Id: I8b1b665e027e925d607fda078cc453a5406f85ea
Signed-off-by: Ping Li <pingli@codeaurora.org>
Add new version 5.0 to CSIPHY and CSID documentation
Change-Id: I7295aa6f23b01304c65ff8de08ac115dc53b9803
Signed-off-by: Sureshnaidu Laveti <lsuresh@codeaurora.org>
Add documentation file for camera drivers into the 4.4 kernel
tree.
CRs-Fixed: 1001183
Change-Id: I6fe3301673eaba9b8b6fa6c4ad8706fa5e979dd0
Signed-off-by: Seemanta Dutta <seemanta@codeaurora.org>
Use the poll_msec set by the driver that registreed an edac device
to define the poll time for how often the edac_check callback function
should be scheduled.
CRs-fixed: 1001207
Change-Id: I973d7fb966cb9f6f9497510df5de000d4f8ffcba
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
The MMSS SMMU needs a few more clocks for correct operation. Add them.
CRs-Fixed: 1000848
Change-Id: Ica34a3a8b514ca4eebc2fb8081db2b167471cd9b
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
The pll min/max supported voltage has changed from 1.8v to 1.2v,
make the necessary change to reflect that.
CRs-Fixed: 1000754
Change-Id: I4dae3d2471bf3a179e810b5d5520eb26f45e26ba
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Enable the UFS and SDHC controllers for cdp and mtp
platform on msmcobalt.
CRs-Fixed: 994739
Change-Id: Ia55c0c59ffad586636a88f42de9fa68656abfe49
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Update the correct clocks and regulators used for UFS.
CRs-Fixed: 994739
Change-Id: Id545c5b8f567e7ccdab1c07af9637848366b49a5
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
On platforms where the power supply for 11AD is external
the wil6210 device can control the rfclk3 clock using a GPIO.
wil6210 driver has to enable the clock during device reset
to guarantee the rfclk3 is on for bootloader activity.
After the wil6210 device is up, the wil6210 driver needs to
leave only the pin clock enabled, to allow the device to
toggle it.
Change-Id: I0f6181d18268f7a2f615155525fbed0f0fe7572a
CRs-Fixed: 986130
Signed-off-by: Maya Erez <merez@codeaurora.org>
Fix type casting in IPv4 and IPV6 driver to avoid compilation
issues for ARCH=um on x86_64.
CRs-Fixed: 996252
Change-Id: Ic3ed8affa2c5bc8fd9b403614f692ab01e1a307a
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Switch the GPU clock to use the gfx_vreg CPR regulator device for
vdd_gpucc-supply. This ensures that the VDD_GFX operating
voltage ends up as low as possible. Also switch the gdsc_gpu_gx
GDSC regulator to use the gfx_vreg regulator for parent-supply.
Add and use a stub regulator for the GFX clock vdd_gpucc-supply
on sim and rumi targets since gfx_vreg may not be usable on these
targets for certain hardware and bootloader combinations.
Change-Id: Ic6536cb90da928ea82d4575922bdf3cb153e5a27
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a VDD_GFX CPR4 controller device which allows consumers to
make voltage corner requests which are then translated to the
minimum possible voltage using the CPR hardware feedback.
Change-Id: Idd5f5380f911b5b5d402b7c19999ce2e300d660d
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a mem-acc-regulator device for the VDD_GFX supply which can
be used to switch the GPU memory arrays into and out of the SVS
voltage usage state.
Change-Id: If2559c619f51bd5a34b7845818ba4c4f8645a975
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Replace the PM8005 S1 stub regulator device with a qpnp-regulator
device. This ensures that consumers physically affect the state
of S1.
Change-Id: I55723cb5a1d49672f243d6911889caa59ec0ee9f
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a dtsi file which specifies the peripherals found in the
PM8005 PMIC chip. Include this new file for msmcobalt boards
since they make use of this chip.
Change-Id: I6620cf1fd5ec4181b7ce79bc97039af954dc324e
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
The subtype register value for PM8005 is 0x18. Add this to the
list of known PMICs.
Change-Id: I5cd316784f1339975a973e63c962fae6cb9db852
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for PMIC FTSMPS 426 type regulators. These have a
4 mV step size and a voltage control scheme consisting of two
8-bit registers defining a 16-bit voltage set point in units of
millivolts.
Change-Id: Id27bf066a014c0a39f47febff2603873050125d9
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for the fuse layout and hardware constraints of the
msmcobalt CPR4 controller which is used to manage the GPU supply
regulator. Also update the cpr3-regulator core driver in order
to support CPR register writing for this device.
Change-Id: I408854a93e820c168551bcfec7d4f87cdbe5d638
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
This is a snapshot of the mem-acc-regulator device tree bindings
documentation file present in the msm-3.18 branch as of
commit 9d555a2ec04c ("regulator: mem-acc: Add support for multi
register configuration").
Change-Id: Iad561ef5bab93f1e82879364639b4a5472e65902
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
