Memory is allocated for the number of available nodes while memory is
freed for the number of all nodes. The memory that is attempted to be
freed when the driver probe fails is out of bounds and leads to a crash.
Fix the looping condition to free the correct amount of allocated memory.
CRs-Fixed: 1006797
Change-Id: I331463e3de8e6ff874995b122aa7415a7da64b31
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
LMH DCVS hardware exports a thermal sensor for each instance. Provide
information about this sensor to msm_thermal.
Change-Id: I59f6c2a5cb552f4462a1ebd3ff8e1c64e7519e2c
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
LMH DCVS hardware block provides hardware based thermal mitigation for
the CPU clusters. There is one block per cluster. Each block exports a
thermal zone, each with one thermal sensor through the thermal
framework.
Change-Id: Ia80616cc97737beadc1c327bcac399d9f7849f25
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
On SoCs that have OSM hardware, use the hardware to setup the CPU
mitigation limits. Having the OSM control CPU frequencies offloads
mitigation from the CPU, resulting in faster thermal mitigation
response.
The LMH DCVS aggregation does not do a max of the min frequency limits.
Therefore to avoid cpufreq voting any lesser than what KTM decides based
on vdd min restrictions, we update cpufreq as well, only if the min freq
has changed.
Change-Id: I2912eaf418d5e7ea4d62a9a55702e02b744a785b
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
The Limits Management Hardware (LMH-DCVS) is a hardware block for
monitoring thermal profiles and taking immediate action to control
temperature without software intervention. The h/w block can only be
configured under secure mode.
The LMH-DCVS block reads CPU temperatures of a cluster by sensing
information from the TSENS hardware and determines the course of action.
When enabled, the h/w triggers when the high threshold is hit for any
CPU in the cluster. The mitigative action is frequency and voltage
control that is provided to the OSM hardware.
The driver registers a virtual thermal zone device for each hardware
instance. The thermal zone device is used to set the thresholds for the
hardware to work on. Once the thresholds are setup and the trip type is
enabled, the hardware functions autonomously. Mitigative action is
completely controlled in the h/w.
Writing to the actual hardware is done through the SCM call.
Change-Id: I70d4bc387717491256fec1ef6bd8cd6a28ea641b
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
phy-ufs-qcom-qmp-v3 needs an additional ref aux clk to be enabled,
add support for the new ref aux clk and make it optional as its not
needed by other phy versions.
Change-Id: I5e04980eb451b193e9c024bfe35383d10d17feff
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
In SSR case the xprt_info pointer is freed without considering the users of
the pointer in TX path will leads to use after free of the pointer.
Use the reference count to keep track of the xprt_info structure and wait
for the all user to complete the task before free the xprt_info pointer.
CRs-Fixed: 999123
Change-Id: I894a877346ff1d395c6f1b06267dfec333cb1024
Signed-off-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
Currently dwc3 driver's probe is doing bus voting. This voting remains
until USB cable is connected and disconnected. Due to this voting, XOSD
is not happening. Fix this issue by removing voting from driver's probe
context and let USB's suspend and resume take care of bus unvoting and
voting respectively.
CRs-Fixed: 1007183
Change-Id: I34f7cbf2aa10b63712e5142f908fa77ae195f5b1
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
The pll supported voltage various per platform, the min supported
is 1.2V and max supported is 1.8V, make the necessary change to
reflect that.
Change-Id: Id93509ddcf298ee076b46703d9a55a5a7ba60638
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Some of registers' offset used with QUSB PHY programming sequeunce are
incorrect. Fix these offset to make sure required registers are
programmed with QUSB PHY.
CRs-Fixed: 1005497
Change-Id: I35751afdc418cd5bd38422d90cedcfd97442a6f7
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Fix compilation issues. Replace deprecated APIs with
the new APIs for 4.4 kernel.
Change-Id: I0cd5adc5c9c6ff9979b6d3a626541e6755029d2f
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Requests that need to go through the ICE must be setup with a key
before and have a key index ready. In cases where the key is not
ready as it is not in the key cache, the ICE 'config_start' callback
returns -EAGAIN and we need to block further requests and call
'config_start' again from a non-atomic context until key setup
is ready and then resume requests handling.
Change-Id: I51ff1e99240386ce533b5ab3f5f024043532b0ad
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
The requests configuration has to be split so clients can inform
ICE laeyr when the request is completed.
Rename the 'config' callback to 'config_start' and add
'config_end' callback.
Change-Id: Ife0b5b62805b827449a1bb1002348db445f03c60
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
When working with multiple files and multiple threads, the following
scenario can occur:
1. File Close -> Key cache removal -> context switch
2. Open new file -> occupy the entry cleaned in 1
-> TZ_ES_SET_ICE_KEY -> context switch
3. Back to 1 -> TZ_ES_INVALIDATE_ICE_KEY
4. Back to 2 -> ICE uses the key that is already invalid
5. Crash due to PARTIALLY_SET_KEY_USED
To fix this, pfk must know when requests using some key are completed.
Only then key removal shall be allowed and until then key invalidation
must wait.
A new callback was added to let clients inform PFK when requests end.
Change-Id: Id7f8a3302fac9fafd1203d8d56ca13d59b45bbd5
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
DM layer allocates pool size of 256 for request based module while
dm-req-crypt internally allocates pool for minimum 16 requests.
Increasing pool size of dm-req-crypt to be consistent with DM layer.
Also, changing GFP mask for allocation from pool, depending upon
whether call is made from atomic context or not.
Change-Id: I9dfeb46520e0d1b1fc6f850a007fce35bdc60d35
Signed-off-by: Dinesh K Garg <dineshg@codeaurora.org>
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
Bus scaling might be disabled in the kernel configuration of
some platforms, in which case initialization will fail due
to the lack of bus scaling support.
Add stub functions to allow initialization without bus scaling.
Change-Id: Ib1edeac145ef1696e657f775cd938839b79dbac0
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
ICE HCI has been updated to v3 so some registers and sequences
were changed. Update the driver to reflect the updated HCI.
Change-Id: I59ba98d86bf0532a7e4c2cfa03d65e57e6a7fdcf
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Andrey Markovytch <andreym@codeaurora.org>
Add MDSS DSI device node for msmcobalt which is needed to drive the
primary display no the DSI interface.
CRs-Fixed: 1000724
Change-Id: Ib2fe58e6c4f0da7a14c10b74328c17fc5abaa7c8
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
At present sched_boost changes scheduler to place tasks on the least
loaded CPU under the assumption both big and little clusters capacities
are same at the same level of frequency. This is suboptimal for the
big.Little system that doesn't have such a symmetrical capacity between
big and little CPUs.
Fix sched_boost to place tasks on the big CPUs for the non-symmetrical
capacity target.
CRs-fixed: 1006303
Change-Id: I752f020acf1a76580edb5cd0e5ad283b62edfeed
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Add QCA and audio slimbus instance entries. QCA entry is disabled
by default and will need to be enabled on applicable boards where
QCA slimbus slave is present.
CRs-Fixed: 998162
Change-Id: I3255322fe3ee9784c688dd4ec6eea69974a4d684
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
List all the resources needed by the MDSS DSI PLL device and add the
corresponding device node for msmcobalt. The DSI PLL is the source for
all the branch clocks needed to drive pixel data over the DSI interface.
CRs-Fixed: 1000576
Change-Id: If851190cc2ec863d8d8a556e1002d7a9f08668d1
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add support to program the DSI PLL on msmcobalt which is needed to drive
the DSI byte and pixel clocks.
CRs-Fixed: 1000576
Change-Id: Ic11a3747a0e008e1f71df91a1a79d33242d2a2a4
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
In case no DT node name, it return error and doesn't go
through other DT node for Bluetooth regulators. To support
multiple Bluetooth chipset, it need to continue to check
remaining DT node since some DT node maybe not available for
some Bluetooth Chipset.
Change-Id: I2427f674ef4889c39580dc2568a6b9566f03f8f2
Signed-off-by: Sungjun Park <sjpark@codeaurora.org>
This change moves QUSB PHY device node from dt source file to st
include file for msmcobalt.
CRs-Fixed: 1003142
Change-Id: I113c42a906b2b455026326a98e4d68bb85c5b10b
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
The hmss_gpll0_clk_src is being sourced off the gpll0 which
uses the cxo_clk_src RPM resource. This causes XO shutdown
to fail. Use the gpll0_ao source instead.
The hmss_ahb_clk_src RCG frequency table is also updated to
use the cxo_clk_src_ao to generate XO frequency.
CRs-Fixed: 1001330
Change-Id: Ic5cba530ea22cd19a20a21f0c33433c5e023debc
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add the following devices that are present in pmicobalt.
- 6 LPG channels from address 0xb100-0xb600 along with LPG_LUT
@ address 0xb000.
- LABIBB regulator device that can support configuring LAB and
IBB modules @ address 0xde00 and 0xdc00.
CRs-Fixed: 1005724
Change-Id: Ic252e83f8a7273796ddc0e42c0ae37f339931499
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Remove unused legacy bus code and APIs
CRs-Fixed: 1006336
Change-Id: I15811b787b54004e1aaba859e4c911be8f9eb285
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Remove write-back and rotator related obsolete code in order to reduce
dead code maintenance.
CRs-Fixed: 987777
Change-Id: I917d9b5b777fb41f3f87213d8d9e6e7ddf73f92c
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Issue: CSIPHY IRQ enabled when kernel recivies possible sof freeze
and will not disable if there is no csiphy release call from backend
which inturn leads watchdog bark.
Resolution: Dump the CISPHY IRQ at the time of possible sof freeze
and disable them.
CRs-Fixed: 996571
Change-Id: I3c6040b81c04660d3a0ac7ed707e1f4b22498dbd
Signed-off-by: Ramesh V <ramev@codeaurora.org>
Use QCOM_BUS_SCALING as opposed to MSM_BUS_SCALING
Change-Id: I23945a040914d55aa483cfec6ef81e7342421f2e
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Enable CONFIG_SCHED_HMP_CSTATE_AWARE in order to optimize task
placement with CPUs C-state. This brings better system performance.
CRs-fixed: 1006303
Change-Id: I18e62015371143bca56396c747eaad3b22c5e3a3
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Update CPU efficiency property for msmcobalt so that scheduler can utilize
for task placement decision.
CRs-fixed: 1006303
Change-Id: Ifb59d6b1fcb1207053438786df2472417a2db93f
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
At present among the same power cost and c-state CPUs scheduler places
newly waking up task on the most loaded CPU which can incur too much of
task packing on the same CPU. Place onto the most loaded CPU only when
the best CPU is in idle cstate, otherwise spread out by placing onto the
least loaded CPU.
CRs-fixed: 1006303
Change-Id: I8ae7332971b3293d912b1582f75e33fd81407d86
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
There are CPUs that don't have an obvious low power mode exit latency
penalty. Add a new Kconfig CONFIG_SCHED_HMP_CSTATE_AWARE which controls
whether CPU C-state is used to guide task placement.
CRs-fixed: 1006303
Change-Id: Ie8dbab8e173c3a1842d922f4d1fbd8cc4221789c
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Update the wakeup placement logic when need_idle is not set. Break
ties in power with C-state. If C-state is the same break ties with
prev_cpu. Finally go for the most loaded CPU.
CRs-fixed: 1006303
Change-Id: Iafa98a909ed464af33f4fe3345bbfc8e77dee963
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
[joonwoop@codeaurora.org: fixed bug where assigns best_cpu_cstate with
uninitialized cpu_cstate.]
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Try and find the min cstate CPU within the little cluster when a
task fits there. If there is no idle CPU return the least busy
CPU. Also Add a prev CPU bias when C-states or load is the same.
CRs-fixed: 1006303
Change-Id: I577cc70a59f2b0c5309c87b54e106211f96e04a0
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
Update ucode workarounds for A5xx GPUs based on new
microcode and hardware changes.
CRs-Fixed: 1000396
Change-Id: I87a1ba9bfc441cad2ed6a6959d07af1cc1e2c7bc
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
Driver is overriding the ep0 request context with gsi driver
context even if it does not intend to handle the setup completion.
This is causing flood of warnings when composite_setup_complete()
is type casting the function driver context as cdev and failing to
match ep0 request pointer with cdev->req. Hence only override
context when driver is overriding the complete call back.
CRs-Fixed: 1003784
Change-Id: I176671ae09f17d920643eeeec8262a6f97856712
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Use "gadget->dev.parent" instead of "&gadget->dev" in the first argument
of dma_zalloc_coherent() because the parent has a udc controller's device
pointer. Otherwise, iommu functions are not called in ARM environment and
allocation is failing.
CRs-Fixed: 1003784
Change-Id: I2ea75b533f857189856840e437a96891eea5699c
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
In case gsi_update_function_bind_params() returns failure
before initializing spin lock for event queue, gsi_bind()
continues further by calling post_event() which acquires
the uninitialized spin lock causing BUG. Hence check for
return value of gsi_update_function_bind_params() before
calling post_event().
CRs-Fixed: 1003784
Change-Id: I0fcad2467d15f311feecf3b9cee9209f7453485c
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Adds support to allocate specific hardware EPs to
GSI enabled endpoints. Creates EP list with names
"gsi-epin" for IN and "gsi-epout" for OUT EPs that
are intended for use by the GSI function driver.
The EPs are reserved from the end of the EP list.
CRs-Fixed: 1003784
Change-Id: I70ebce8c2717baaea38f7b6235976d8a522eb9fd
Signed-off-by: Devdutt Patnaik <dpatnaik@codeaurora.org>
This allows configuration of event buffers for GSI based
hardware accelerated endpoints.
Change-Id: If9ae84c0de214bcb5057d14a6960b6fb528c6c14
CRs-Fixed: 1003784
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Add additional event buffers for GSI based hardware accelerated
endpoints and its related configuration.
CRs-Fixed: 1003784
Change-Id: Ibedf73690040b8bd872f5621835680a66c22e265
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Enable smart prefetch control for xDCI channels.
This is done by configuring the channel scratch in GSI.
Change-Id: I9a301da3c5426649b40069103d545e50bc75aad2
CRs-Fixed: 1004467
Signed-off-by: Gidon Studinski <gidons@codeaurora.org>
Enable smart prefetch control for MHI channels.
This is done by configuring the channel scratch in GSI.
Change-Id: Icff18699ce96e224d6f58b8aadce006f3d5210ee
CRs-Fixed: 1004468
Signed-off-by: Gidon Studinski <gidons@codeaurora.org>
