Currently, PCIe bus driver on mdmcalifornium does not
have support for ARM32. Thus, add the necessary changes
to support ARM32 for PCIe on mdmcalifornium.
Change-Id: I6c72debd9ea65b7abb70ce4d5568c972ba786c11
Signed-off-by: Tony Truong <truong@codeaurora.org>
Not all targets will have a dedicated line for each PCIe
interrupt. On these targets, some PCIe interrupts will be
aggregated into one line. Thus, add support to handle
aggregated interrupts.
Change-Id: I4f5be73718d4a4ae8a3de142579f24a7113fe086
Signed-off-by: Tony Truong <truong@codeaurora.org>
Based on si learning, new PCIe PHY settings improve the overall
stability of PCIe PHY on MSM8996 v3 and on v4. Thus, update the
PCIe PHY sequence for MSM8996 v3 and v4.
Change-Id: Ia1ab0af4c4dcf483d3b3dc05b7b13003de788f40
Signed-off-by: Tony Truong <truong@codeaurora.org>
The counter for the number of active root complexes
determines when PCIe common PHY should be powered on/off.
To avoid conflicts and a stale counter, add locks to protect
the access to PCIe common PHY.
Change-Id: I18ec54e52e804eb132f9c5c0270455dbc9187151
Signed-off-by: Tony Truong <truong@codeaurora.org>
Not all endpoints require PCIe WAKE support.
Therefore make PCIe WAKE GPIO optional.
Change-Id: Ifc5a84204cde42881a127b4715727c290ee24450
Signed-off-by: Tony Truong <truong@codeaurora.org>
In addition to having outputs to kernel log, PCIe
debugfs messages should also be captured in IPC logging.
Therefore, add a new IPC logging label and update the
existing calls to do so.
Change-Id: I2ab6a6549575c4e2de2f1ef0756328f4b6f6a178
Signed-off-by: Tony Truong <truong@codeaurora.org>
PCIe bus driver can now use devicetree to help distingush
which PCIe QMP PHY version is being used. This will allow
PCIe bus driver to choose the correct PCIe PHY sequence.
Change-Id: I74c67431b75292bb1db3e4b97d89d69de9b6f11b
Signed-off-by: Tony Truong <truong@codeaurora.org>
Current PMIC API call to disable CX rail does not remove
PCIe power vote. Add another API call to successfully
remove vote when releasing this resource.
Change-Id: I5203203e10e8e690745768c241e92d298b87cc4b
Signed-off-by: Tony Truong <truong@codeaurora.org>
To improve PCIe PHY stability, add a delay between
the write of power down and sw reset register on
MSM8996.
Change-Id: If09390bff59e0922cb891c7bac823c11361fca83
Signed-off-by: Tony Truong <truong@codeaurora.org>
In order for PCIe to reliabily work in SVS mode,
the PCIe PHY RX clock needs to be slowed.
Change-Id: Ic6edf487011ef4ac71d486210b1f6176e2142551
Signed-off-by: Tony Truong <truong@codeaurora.org>
Increase the wakeup delay time for PCIe aux clock on MSM8996
to improve PCIe stability when waking up.
Change-Id: I2909e80a2c79b4f17ca39c39d899de08b67d4120
Signed-off-by: Tony Truong <truong@codeaurora.org>
Each PCIe client requires different CX power levels
to maintain functionality. This change gives each
PCIe root complex the ability to vote for CX power
levels.
Change-Id: If027c79220253a60837c3d52202fb5ec4cc3451e
Signed-off-by: Tony Truong <truong@codeaurora.org>
New QMP PHY sequence for 1MHz aux clk for PCIe
on MSM8996. Therefore, update the PCIe PHY
sequence.
Change-Id: I2b3746cc9d6ab6b491fa7404ae54fefbf36df905
Signed-off-by: Tony Truong <truong@codeaurora.org>
There are unnecessary cleanup code which alters the descriptor
of a Synposys MSI IRQ and this causes the IRQ to be unusable
afterwards. Remove the unnecessary cleanup code for Synopsys
MSI so that the IRQ will remain functional.
Change-Id: I87221f9a59d014df21af251277866c511c5375eb
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add PCIe support for 3.18 kernel. Added enumeration,
interrupts, and hardware configurations support for
PCIe.
Signed-off-by: Tony Truong <truong@codeaurora.org>
Increase the Ipeak request for each PCIe LDO based
on updated settings.
Change-Id: Ie3af6462dac68252b339595e350e393079a89bb9
Signed-off-by: Tony Truong <truong@codeaurora.org>
SMMU requires PCIe to provide a SID for each of its endpoint
so that the endpoint can successful transaction on the bus.
This change adds the support for PCIe bus driver to calculate
a SID for its endpoint and give it to the SMMU driver.
Change-Id: I52099bbfed0a38c75b0277b0f58f45f6e6559695
Signed-off-by: Tony Truong <truong@codeaurora.org>
In the case where the Root Complex fails to retrive a valid
index, the exit code fails to handle this correctly. This
change corrects the way the exit code handles invalid root
complex indexes.
Change-Id: Ie832fec1be2b05dea05b8917348a1c08cdc1d681
Signed-off-by: Tony Truong <truong@codeaurora.org>
Some EP requires additional GPIO to be enabled for link training.
Add the support in PCIe Bus Driver to manage this GPIO.
Change-Id: I837edae478779fdaf3e94c70a0a031f9d0580a77
Signed-off-by: Tony Truong <truong@codeaurora.org>
PCIe on some targets require the iommus device tree entry.
Therefore, add this device tree entry to the PCIe
documentation.
Change-Id: Iec6c4cfcd5e51d6aa1259bb826fe60d131072170
Signed-off-by: Tony Truong <truong@codeaurora.org>
There are new PCIe PHY settings that have been updated
to improve performance and stablilty. Therefore, update
the PCIe PHY sequence on MSM8996.
Change-Id: If321471c51ff6a91595b68bd2cae08c8c043d6bb
Signed-off-by: Tony Truong <truong@codeaurora.org>
To support more accurate benchmarks, add entry and exit logs
for PCIe functions.
Change-Id: I49f27263722adfaa8ae3973f242faa6a589d3358
Signed-off-by: Tony Truong <truong@codeaurora.org>
To support PCIe MSI on 3.14 kernel, the client's host
driver must use the QGIC IRQ number to request/enable
the interrupt while the client's firmware must use
the SPI number to trigger the interrupt. Therefore,
add this logic in PCIe bus driver to support MSI
interrupts on 3.14 kernel.
Change-Id: I165022281c9e795be8c5e2e4a4faa34d4c004a45
Signed-off-by: Tony Truong <truong@codeaurora.org>
After writing to a PCIe PHY debug register, the wrong
PCIe PHY status register is being read back. This change
corrects the PCIe PHY status register that is read back.
Change-Id: If360aa6f9b4530e4c07acfcc1af684c6d7ecc234
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add PCIe support for thulium. Added enumeration,
interrupts, and hardware configurations support for
PCIe.
Change-Id: I48b2fc8a51303a6aea7b1b2a97c4de25f19ded4c
Signed-off-by: Tony Truong <truong@codeaurora.org>
When searching for the endpoint's capabilities register,
check that the value from the register read is valid.
Change-Id: Ia64de3c75618ca0a51aa4588ac97f2fcb26d8829
Signed-off-by: Tony Truong <truong@codeaurora.org>
When reading shadow registers, the wrong value is being
recovered for root complex L1 register. Currently,
the value being recovered is a shadow of the endpoint's
L1 register. This change will recover the correct shadow
value for RC L1 register.
Change-Id: I82b1810ef8761de90b350743cdd9b24a74efb62f
Signed-off-by: Tony Truong <truong@codeaurora.org>
There is an extra identical call made to check if aux clk
is supported base from PCIe device tree node. There is no
need to do this check twice; therefore, remove the duplicate
call.
Change-Id: If705e98e637287969d68ea2241e62447aa505eb0
Signed-off-by: Tony Truong <truong@codeaurora.org>
Not all the testcases for debugfs needs the calculated offset
of an endpoint's capability register. Therefore, only calculate
the offset of an endpoint's capanility register if that testcase
needs it.
Change-Id: Iffddcea682d8c9344f51a04b57f60ba906b01dc6
Signed-off-by: Tony Truong <truong@codeaurora.org>
When the clients want to enable common clock for the
endpoint, also enable it for the root complex.
Change-Id: I55d5a69be0746a745b073051452d45a38d0a4e65
Signed-off-by: Tony Truong <truong@codeaurora.org>
FSM9010 requires a different PHY sequence. Therefore,
this change adds the PCIe PHY support for FSM9010.
Change-Id: Ic98860d3ac1f7b644b76064032f399f070fc9b47
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add support to enable the clock power management for the
endpoint.
Change-Id: I02bebfeb5d32eb8e1f75ee5feb4c4fff956ece66
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add support to enable the common clock configuration for the
endpoint.
Change-Id: I9f6c33eb6cfa032837a07e437f349a7c1a60704c
Signed-off-by: Tony Truong <truong@codeaurora.org>
The start address of the capability register varies
depending on the endpoint. This change calculates the
endpoint's capability register offset instead of using
a fixed one.
Change-Id: I28a97d316aee8c34afe313838b91fcc06af0847f
Signed-off-by: Tony Truong <truong@codeaurora.org>
In the case of multiple endpoints connected to a bridge,
PM logic is not present. Therefore, this change adds
PM support for when there are multiple endpoints on a bridge.
Change-Id: I5a1876db85d0d161ae537a09a508a93b5099aa56
Signed-off-by: Tony Truong <truong@codeaurora.org>
This PCIe bus driver snapshot is taken as of msm-3.10 commit:
803998b (Merge "ASoC: wcd: don't set autozeroing for conga")
This change adds the PCIe bus driver and its dependecies from
msm-3.10 to msm-3.14. All the files are as is from msm-3.10.
No additional changes were made.
Change-Id: Ia1a2d0eea0cc87c16357c95bfcc4df72e910cd34
Signed-off-by: Tony Truong <truong@codeaurora.org>
Enable CONFIG_RTC_DRV_QPNP as power_on_alarm_init is added by
change : I781389c658fb00ba7f0ce089d706c10f202a7dc6
Change-Id: I48bc69e2215e45e0c5c7bc8aa2c489fca995c201
Signed-off-by: Mao Jinlong <c_jmao@codeaurora.org>
Android does not support powering-up the phone through alarm.
Set rtc alarm in timerfd to power-up the phone after alarm
expiration.
Change-Id: I781389c658fb00ba7f0ce089d706c10f202a7dc6
Signed-off-by: Mao Jinlong <c_jmao@codeaurora.org>
Add the rtc irq support for alarmtimer to wakeup the
alarm during system suspend.
Change-Id: I41b774ed4e788359321e1c6a564551cc9cd40c8e
Signed-off-by: Xiaocheng Li <lix@codeaurora.org>
This snapshot is taken as of msm-3.18 commit 95a59da3cf
(msm: hdcp: proper state sanitization for different versions)
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Save gic-v3 distributor registers on panic. Allows for inspection of
gic-v3 state at the time of a panic.
Change-Id: I3236577161abab4e292a01254e1e1ecb50bb38de
Signed-off-by: Cassidy Burden <cburden@codeaurora.org>
Gic-v3 did not log IRQs in RTB like gic-v2. Thus add the LOGK_IRQ log
before calling the IRQ handler like gic-v2.
Change-Id: I46a5951e733a05b9a7d5d6323568fa800dfb5d62
Signed-off-by: Cassidy Burden <cburden@codeaurora.org>
[abhimany: resolve minor merge conflicts]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Add support to configure ITS registers only if higher
exception levels have not already configured them.
Change-Id: I45eaa51e56e034d011cf41d8b924fb674f63447d
Signed-off-by: Hanumant Singh <hanumant@codeaurora.org>
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
[abhimany: resolved minor merge conflict]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
As per the GICv3 architecture spec section "Observability
of GIC Register Accsses", architecture execution of the "DSB"
gurantees that last interrupt identifier read from ICC_IAR{0,1}_EL1
is observable by the top-level Distributor and by accesses from
any processor to the top-level Distributor.
Same comment goes for the ICC_PMR_EL1 and ICC_SGI1R_EL1 too.
CRs-Fixed: 960754
Change-Id: I9c7bcdee51f71d369e2a6f04faf7a22c3c1381bc
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
[abhimany: relocate mb()'s to header files]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Some SOCs(System-on-chip) S/W configurations restricts the access
to particular set of the GIC registers to prevent invalid
accesses for the security reasons. Provide a configuration
option for the GICv3 driver and also restrict the access
of the GICR_WAKER registers from the non-secure world.
If this Kconfig option is not selected then it means that
access control configuration is enabled from the secure world.
CRs-Fixed: 958251
Change-Id: I91f06484b6b6bf58d05e6b621ee84610a71fe3e7
[abhimany: minor merge conflict resolution]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
A user space application is planned to support feature for
synchronized timestamp among debug packets across peripherals.
As part of the feature, it is responsible for providing physical
timer count value to user space. If memory mapped timer is used
in ARM arch, Usersapce can't read the physical timer count directly
with a MRCC ASM instruction. So Kernel traps the instruction and
returns the physical timer count.
Change-Id: Ia3f0d9c8c06ca9e2204187890c0c57c8640e4f7e
Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
[abhimany: minor merge conflict resolution]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
A user space application is planned to support feature for
synchronized timestamp among debug packets across peripherals.
As part of the feature, it is responsible for providing physical
timer count value to user space. So Enable user access to the
physical counter in cp15 register.
Change-Id: Idf7f6375713d842925e6f72a4b1fb98a7168726d
Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
