Turning off pll digital block before link clocks leads
to clock status stuck ON. Ideally, DSI driver should
first stop the lanes, followed by link clock stop
and pll disable. This change implements these
recommended sequence for both DSI controllers.
Change-Id: Ibe3061a65bad2dbfdffd9505d469f10f62a6e39d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
msm8996 v2 pll needs different ldo configuration in DSI
pll compared to v1 target. This changes updates the DSI
pll driver to support this new configuration.
Change-Id: Idccfad2e388273a15b45a0e8bb822513fcbbe70e
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Pll unlocked due to wrong pll fractional divider calculated.
Pll fraction divider should be reminder of 2^20 after vco
rate divided by reference clock rate.
Change-Id: I9e4c2e3c0631e533d114c3e6acf65b71b9bf00d2
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
As part of 3.18 upgrade, remove support pll support for all
other targets except msm8996.
Change-Id: Idc778ccba25ce22ad7e418c45f2bd8d21ccb95e8
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Export stereoscopic 3D modes supported by the driver to the
userspace.
Change-Id: I9992fc10abeca9cf48a9cca5efd404ec0693bb72
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
To improve the timing margin, lane mode selection
needs to be written during the HDMI PHY startup
sequence. This prevents a timing failure when
VDDCX or VCCA_CORE are applied rather than the
nominal value.
Change-Id: I2ed54f63903a473eca12fb4d8f3b542585397dae
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Update HDMI PLL calculation for thulium. These changes are based on
latest settings from PHY team.
Change-Id: I9ab20c4101ff7cbebab61c35553b3e9d4799019f
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
During split display case, pll-1 share vco output of pll-0.
Therefore pll-1's related clock dividers need to be
configured along with pll-0.
Change-Id: I98744ec0b8a5bea952f41754788ba44d824d3373
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Remove references to 14nm and replace them with thulium.
Change-Id: I8a3a86d3510bea71f19003bebe89318c2fb399d4
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
Implement dsi related clocks framework so that dsi
vco pll related function be called to output correct
vco rate base on byte clock rate. After that pixel
clock rate can be achieved through MND setting.
Change-Id: I819f9fcb8afd9430f131679434c4da34641ce3f8
[veeras@codeaurora.org: As part of 3.18 upgrade,
remove all non-display related code from this commit
include/dt-bindings/clock/msm-clocks-thulium.h]
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
To completely shutdown pll 1, power down sequence has to be
called. This is different from the old sequence where disable pll
sequence acturally turn off pll.
Change-Id: Ia8b9adb8f78241e34420c0966c3c25b7684b1262
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
One subset of pll common block setting registers need to be programmed
for both pll 0 and pll 1 to prevent current leakage.
Change-Id: I1ba621f21b49e0e55c3840b281ca9323130465a2
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
This change is corresponding to the update from h/w documentation.
Change-Id: I74ac06ce0cd1b0a8b52be6fa7dab123ebb2fc79e
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
The new sequence is intended to improve pll locking time. This patch
is to implement locking pll using stored codes and bypassing
calibration.
Change-Id: I1a26843b5d784984dff4fee0e17841cfc1be37cc
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
readl_poll_timeout and readl_poll_timeout_atomic really accomplish the
same thing, just in different contexts. Unify their interfaces to
reduce cognitive load on developers and code reviewers.
Change-Id: I319db7cb3894c66447b3337c6802b723a38b3544
[veeras@codeaurora.org: As part of 3.18 upgrade,
remove all non-display-related code from this commit
arch/arm/mach-msm/clock-mdss-8974.c
drivers/iommu/arm-smmu.c
include/linux/iopoll.h]
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Added support for new HDMI pll present on thulium. Implemented dynamic
calculator for pll settings.
Change-Id: Ib0b728d9ffb44b753657292e387ee7b44e854122
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
The new sequence is intended to improve pll locking time. This patch
is part of new sequence in pll driver side.
Change-Id: I09760d52db12deda0c0b4bf700db301cde8a05f1
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
[imaund@codeaurora.org: Resolved context conflicts]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
Parse HDMI PLL string for msm8992 to set the PLL
interface type to 20nm HDMI PLL.
Change-Id: I7fe187148395d530871dd85ccd59f0645f894096
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Add 8992 to 20nm pll supported devices.
Change-Id: Ic5ca0dc72b83da7a559cfbad1c748b25d1542919
[veeras@codeaurora.org: As part of 3.18 upgrade,
remove all non-display related code changes from the commit
include/dt-bindings/clock/msm-clocks-8992.h]
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Introduce minor delays in HDMI PHY sequence to ensure that
PHY is ready before failing with a timeout.
Change-Id: I8e9adf542b60e63c0c28d314afd5ac61fa64d1b2
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
TZ introduced a recent change which mandates the scm call
before accessing the pll registers. So, when continuous splash
is disabledin bootloader, the scm call is not made and it causes
device crash when the pll driver tries to access the registers.
This change makes it return with a disabled handoff clk from the
pll driver when continuous splash is disabled, thus not accessing
the pll registers at this point.
Change-Id: Ic487ef733f889d463d149ee347667cd8eb04084f
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Change the VCO frequency range to avoid display fading issues.
Add code to change the PLL dividers to match the new
VCO frequency range.
Change-Id: Iec62f6be26d47cdfd8b2acb895f2e80d57164833
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Automatically calculate the register
values needed for HDMI PLL based on the
pixel clock.
Change-Id: I6fbe519e0316c3f9cc12cd0afd5aa08a90deed7d
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Some of the macros in iopoll.h might be a tad verbose or
redundant. Several of the "verbose" macros are not used anywhere in the
kernel. Based on feedback from upstream, rip out the extra "wrapper"
macros and convert callers (if any) to the lower-level ones.
Also change the `_noirq' suffix to the more idiomatic `_atomic'.
The following semantic patch was used to help identify and make the
necessary changes:
@@
expression addr, val, cond, timeout_us;
@@
- readl_tight_poll_timeout(addr, val, cond, timeout_us)
+ readl_poll_timeout(addr, val, cond, 0, timeout_us)
@@
expression addr, val, cond, max_reads, time_between_us;
@@
- readl_poll_timeout_noirq(addr, val, cond, max_reads, time_between_us)
+ readl_poll_timeout_atomic(addr, val, cond, max_reads, time_between_us)
Change-Id: Ibdb054ded59d777f38f594a2f09a12c64abdb059
[veeras@codeaurora.org: As part of 3.18 upgrade, removing all
non-display related code from this commit.
arch/arm/mach-msm/clock-mdss-8974.c
drivers/clk/msm/gdsc.c
drivers/iommu/msm_iommu-v1.c
include/linux/iopoll.h]
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Add changes for DSI PLL clock driver support for msm8909. Add
the compatibility string of the DSI PLL handle so that the
detection and support of DSI PLL driver for 8909 happens
dynamically.
Change-Id: If1fb96982433f90c5b82dda8686b7284825bcd09
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
Reducing delays in HDMI clock enable to prevent
the thread from being held in the realtime process
and hogging the CPU. Updated delays are provided
after further hardware testing. With the added
microsecond delay in the timout loop, C and PHY
ready should occur well before timeout.
Change-Id: Ib36a06e5309f3f8ba9e4013d08ca2ed108457beb
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Setup DSI 1 PLL clock heirarchy. This is needed for instances
where we need to turn off the second pll in case of current
leak issue.
Change-Id: I694af1fa9591b2345709687c9e7b1d69f15b56a9
[veeras@codeaurora.org: As part of 3.18 upgrade,
removing changes in include/dt-bindings/clock/msm-clocks-8994.h
from this gerrit]
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The second DSI PLL is consuming power when it is in reset
state. Configure the needed registers to shutdown the
second DSI PLL properly even though its not been used.
Add these register configurations whenever mdss gdsc
is toggled.
Change-Id: I008bc102795ccb5991bf4b61545c2d672b453392
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Boot loader enables resources for continuous splash
screen feature and leaves it on when kernel boot up.
MDSS PLL driver adds vote for for these resources in
kernel. Some other driver can also request same resources
and disables it in failure case. This will fade out
splash image on screen. Initializing pll driver
at subsystem level adds vote for resources at early
stage.
Change-Id: Icb80c73e185461a49f682a80ab0578883640e803
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Implement the software mux to byte clock and pixel source clock
with shadow implementation of PLL clock. This is used for
configuring the dynamic refresh pll registers.
Change-Id: I9c84cb76d040c5df7361291b6e1fc0fe69dc214f
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Add support for parsing dynamic refresh register base
for register programming.
Change-Id: I0f23f3c6c01e2ef47fec5048ae0c8ebf31566b61
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Add code to support DSI auto PLL calculator for 8994 platform
that uses 20nm physical layer. Update the PLL configuration
and DSI PHY regulator configurations to the recommended
settings.
Change-Id: Ia3d7042d537539491317f99d7bcc2c480f850216
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add support for HDMI PLL on msm8994.
Support is added to register this new clock
driver. Also modify makefile to compile new
20nm PLL source and add support for registering
PLL clock driver for 20nm HDMI PHY.
Change-Id: I57421ac638075358c46ddd938e441a8e525f3a5a
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Fix the debug clock names to match with proper clocks for
msm8994. These clocks are part of 20nm PHY PLL configuration.
Change-Id: I709d6df80330702304b91d76ec2cad0a7f494c1e
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add support for new 20nm PLL clock driver to handle
different DSI panel resolutions. Add seperate files
to support this new 20nm PHY PLL block.
Change-Id: I4ee5309449f317daddba7106cb8e1829fd6e76cf
[veeras@codeaurora.org: As part of the 3.18 upgrade,
removing all the msm/mdss display related changes from this
commit as it was already updated during that msm/mdss folder update]
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change adds the DSI PLL clock driver support for
msm8939. Add the compatibility string of the DSI
PLL handle so that the detection and support of DSI
PLL driver for 8939 happens dynamically.
Change-Id: Iaa4be3541ce938816d5b9552b685ce05e7cdab64
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
At present, the PLL resources are updated based on the
enable/disable parameter that is passed to the API. Add
support to update the PLL resources based on a ref count.
This avoids additional delay due to repeated enable/disable
of the resources and also maintains proper state of the PLL
resources.
Change-Id: I39b7ee2b33acb81acdb7dc1f4f387dc71381a464
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Re-organize the DSI PLL driver code and split it based on
the DSI PLL HPM/LPM mode. Add a common PLL util file to use
the APIs which are common for both PLLs. Update the DSI PLL
enable sequence with the recommended settings for LPM mode.
Change-Id: I3f86554522e16579d5c2eccab976136c7afb0dd2
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Increase both edp pll's PPM and idle time setting to fix
edp pll unlock problem during stress test.
CRs-Fixed: 614017
Change-Id: Ic8315fc77dd002e709a9b215b22cbf498edaf30b
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Remove mutex and ref count variables that synchronize the
resource enable and disable calls since the regulator
and clock drivers take care of maintaining the ref
count for each resource. Also, remove resource enable
and disable calls from mux_set_rate/mux_get_rate/clk_enable
context of the DSI branch clocks to avoid warnings.
Change-Id: Ieb32141156afcce008b3555af476c20f888f064b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
This change adds the DSI PLL clock driver support for
8916. In addition, it adds support of DSI PLL programming
of different MDSS revisions using the same DSI PLL driver.
Also rename the compatibility string of the DSI
PLL handle so that the detection and support of DSI
PLL driver for 8974 and 8916 happens dynamically.
Change-Id: I169ebeaf23e4be8ff4b533fce1057144edd8b692
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Do not include msm_iomap header file because MDSS pll
driver is not using it.
Change-Id: Ibe47a7d643bd6c9c5e0a69aad1ff0cc44da09211
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
PHY registers are not updated during MDSS HDMI
pll configuration due to wrong memory mapping.
It also leads to crash when user connects the
HDMI cable with target. This change fixes the
memory mapping for PHY and also adds the missing
register configuration entry for HDMI pll.
Change-Id: Ie81045fed320993fbab6b02bec6b2b82e5b5d495
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Each display output interface such as eDP, HDMI and
DSI are clocked by different pll clocks to support
various displays at different resolution simultaneously.
The mdss pll driver handles all these display output
interfaces' pll clocks separately. It also handles their
resources through dtsi configuration.
Change-Id: I1de2ae9a0549de901a6c82ea489199a722344dc4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Export DSI control properties in debugfs nodes. DSI commands
and properties can be get and set by reading and writing
debugfs nodes which helps debug and panel bring up instead
of changing dtsi files.
Change-Id: I768a85447d88167894c46eb0770d2644910f84cd
Signed-off-by: Xu Yang <yangxu@codeaurora.org>
[cip@codeaurora.org: Remove u32 typecast for
debugfs_create_bool]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Export panel properties in debugfs nodes. Panel property values
can be get and set by reading and writing debugfs nodes, which
helps panel bring up and debug instead of changing dtsi files.
Change-Id: I2c658c4bf2a0f0c0713df0ab8898380227f0a03b
Signed-off-by: Xu Yang <yangxu@codeaurora.org>
[cip@codeaurora.org: Resolved merge conflicts,
remove u32 typecast for debugfs_create_bool]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Enabling CRCB ordered chroma formats. This was a valid working
formats in legacy rotator code, enabling same functionality
in new rotator validation check.
Change-Id: Iecc96861b5c7cd0a2929d222de3514d4d8f71d44
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
MDP core clock has been turned into a voter clock and can now
be directly voted for. No longer need a reference to source clock.
Change-Id: I7c9efc1d56d54840cea43776f53505a32a92f7a5
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
